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Portmaster Adapter/A
Multiport Adapter Model II
Electrical Interface Board Information
for
Hardware Developers
Second Edition (August 1996)
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© Copyright International Business Machines Corporation 1991. All rights reserved.
Chapter 2. Interface Board Architecture
Chapter 3. Functional Interface
Chapter 4. Power Availability and Electrical Considerations
Chapter 5. Thermal Considerations
Chapter 6. Mechanical Hardware
Chapter 7. Diagnostic Support Strategy
References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates.
Any reference to an IBM licensed program or other IBM product in this publication is not intended to state or imply that only IBM's program or other product may be used.
The following terms, DENOTED BY AN ASTERISK (*), used in this publication, are trademarks or service marks of IBM Corporation in the United States and/or other countries:
IBM Personal System/2 Portmaster OS/2 Operating System/2 Micro Channel
The following terms, DENOTED BY A DOUBLE ASTERISK (**), used in this publication, are trademarks of other companies as follows:
Intel Intel Corporation Signetics Signetics Corporation Zilog Zilog Corporation
This publication contains hardware development information and techniques that may be applied to the design of an Interface Board that attaches to either the IBM* Realtime Co-Processor Portmaster* Adapter/A or the IBM Realtime Co-Processor Multiport Adapter, Model II.
Note: Throughout this publication, the general term co-processor adapter is used to designate either feature card named above. Unless otherwise stated, the information contained herein applies to both co-processor adapter cards.
The objectives of this publication are to provide the following for the Interface Board:
The information in this publication is intended for hardware designers, engineers, and individuals with a knowledge of electronics and/or programming who wish to design an Interface Board that attaches to the co-processor adapter.
It is assumed that the reader is familiar with the co-processor adapter, the applications in use, and programming. Therefore, terminology is not explained herein, except for terms that may be specially implemented.
The information contained in this publication is organized as follows:
This publication contains instructions for installing and setting up the Realtime Interface Co-Processor Portmaster Adapter/A, as well as the optional Interface Boards and cables.
This publication contains instructions for installing and setting up the Realtime Interface Co-Processor Multiport Adapter, Model II, as well as the optional Interface Boards and cables.
This library is used to isolate and repair a faulty field-replaceable unit. It provides instructions for problem isolation to help identify a faulty unit. Removal and replacement procedures are presented to complete the repair.
This publication describes the programmer interfaces to the Realtime Control Microcode.
This publication provides information necessary to interface the co-processor adapter through the system unit DOS. It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode DOS Support software.
This publication is a productivity aid that provides the system developer with a variety of services to ease the writing of systems applications for the Realtime Interface Co-Processor family of adapters. It includes numerous task, event, resource, and communications services that allow the system developer to concentrate on the application instead of the system.
This publication provides information necessary to interface the co-processor adapter through the system unit Operating System/2* (OS/2*). It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode OS/2 Support software.
This publication is a productivity aid which allows programmers to develop code for the co-processor adapter in the C programming language. It explains the C interface routines and the method of compiling and linking C tasks for the co-processor adapter.
One or more of the following publications might be needed for reference when using this publication.
Interface Boards can be built to attach to either the IBM Realtime Interface Co-Processor Portmaster Adapter/A or to the IBM Realtime Interface Co-Processor Multiport Adapter, Model II. The Portmaster Adapter/A allows Micro Channel* connectivity and Bus Master capability; whereas, the Multiport Adapter, Model II allows connectivity to the PC/AT bus. The mechanical design of both co-processor adapter cards is such that one Interface Board (IB) can install on either co-processor adapter card. The mounting differences are few; only a bracket and minor hardware mounting changes are required. The distance between the Interface Board and the co-processor adapter card varies, depending upon which co-processor adapter card is used. Refer to Chapter 6. "Mechanical Hardware" for specific values.
With the exception of processor speeds, system clocks, and overall DMA performance, the interface is the same for both co-processor adapter cards. The Portmaster Adapter/A operates at a clock frequency of 12.5 MHz, and the Multiport Adapter, Model II operates at a clock frequency of 10 MHz.
A co-processor adapter card has an 80C186 microprocessor for central processing of data on the card. A partial 80C186 system bus is provided at the IB interface. See Figure 1. This partial system bus includes 16 bits of address, 8 bits of data, and various control lines.
A co-processor adapter card can support various sizes of dynamic random access memory (DRAM). Up to 2M bytes of DRAM are supported on the Portmaster Adapter/A card, and 1M byte is supported on the Multiport Adapter, Model II card. This DRAM area can be accessed by the 80C186; it also can be accessed through the IB interface using the DMA Peripheral Interface Chip (DMAPIC). For the Portmaster Adapter/A card, the DRAM can be accessed from the Micro Channel via the RAM Controller and Bus Master Interface Chip (RCBMIC). For the Multiport Adapter, Model II card, the DRAM can be accessed from the PC bus using the Shared Storage Interface Chip (SSIC).
The DMAPIC has 16 independent DMA channels that are fully programmable. Eight of these DMA channels are hard-wire dedicated to the two Signetics Dual Serial Controller Chips (DUSCCs), SCC0 and SCC1, located on the co-processor adapter card. These two DUSCCs provide four serial ports of data and modem control signals. The data and modem control signals are available at the IB interface, and can be conditioned with drivers and receivers to provide connectivity to various electrical communication interfaces. See Figure 2. The remaining eight DMA channels are available to service various IB devices, such as two additional DUSCCs.
The DMAPIC has six sets of interrupt/interrupt acknowledge lines, four of which are used on the co-processor adapter card; the remaining two lines are available at the IB interface.
Chip select lines have been provided specifically for additional DUSCCs. These lines are available at the IB interface, and may possibly be used to select devices other than DUSCCs on an IB, if carefully used.
Two Zilog Counter/Timer Parallel I/O Units (CIO chips, CIO0 and CIO1) reside on the co-processor adapter card. The CIOs each have two parallel 8-bit I/O ports that are wired directly to the IB interface. The bits of these ports are bidirectional and individually programmable. In addition to the four 8-bit ports, CIO1 provides a 4-bit port which is accessible at the IB interface. The CIOs also have various timers that can be accessed via the ports.
Various other chip select lines are provided for I/O space that has been allocated for use on an IB.
A general-purpose register (Enables Register) is provided on the co-processor adapter card. The outputs of this register are wired to the IB interface and function as general-purpose control lines.
All Interface Boards must be assigned a single-byte ID by the Boca Raton MSP Co-Processor Hardware Development Group. Contact your IBM Marketing Representative to obtain an Interface Board ID assignment. It is recommended that all IBs implement IB ROS as described in this document, and that the ID be written to an architected address within this ROS. In certain instances, where an IB ROS is not implemented, the hardware must provide the facility to read the ID from I/O address 86h.
If the ID is implemented in IB ROS, it will be located in the Header section, and can be accessed by an I/O read to address E000h. This implementation also requires that a read to I/O address 86h result in a value of FFh. A chip select that decodes 86h has been provided; see "Timing Diagram for ROS and RDID86 Chip Select Signals".
The IB ROS provides 4KB of address space, which is accessible in I/O space from E000h to EFFFh. Structures, which are used to provide information about the communication ports, have been architected in the IB ROS. The data contained in these structures is then incorporated into the Port Configuration Descriptor (PCD), for use by the Realtime Control Microcode and Extended Services. The ROS also contains a mechanism for executable routines; see "Read Cable_ID Executable Routine".
A detailed discussion of PROM implementation is provided see section Prom Implementation and Other Uses.
Figure 1. Block Diagram of Co-Processor Adapter
+--------+ +-+ +----------+ +-----+
| | | | |Gate Array+-------Address------------>| D |
| |<---Data----------->| |<----->| | | R |
| Micro | |D| | RAM |<------Data--------------->| A |
|Channel | |r| |Controller| | M |
| or | |i| | & |-------RAM Control-------->| |
| PC Bus |<---Address-------->|v|<----->|Bus Master| +-----+
| | |e| | Interface|
| | |r| | (RCBMIC) |
| | | | | |
| |<---Control-------->| |<----->| (Note 2) |
| | | | +--+---+---+
| | +-+ ^ ^
+--------+ | |
+-+ V | +---------+
|8|<-Control----+--------------------------+---|----------------------------------------->| |
|0| | | | |
|C| | V | |
|1|<-AD0-AD15,--|--+---------------------------+-----------------------------AD8-AD15 --->| |
|8| A16-A19 | | +-+ +----------------------BAD0-BAD7--->| |
|6| | | |D| | 1 | I |
| | | | |r| | 0+---+ Data & Modem | B |
|C+------+ | |<------>|i| BAD0-BAD7 | +-+-+ | Control | |
|P|<-+ H| | | |v|<----------------+-----+---+-------->| D | |<------------->| I |
|U| H| O| | | |e| ^ | +---->| U | | | n |
+-+ O| L| | | |r| | | | +->| S | | | t |
L| D| | | +-+ V | | | | C | | | e |
D| A| | |<---------------+ +-+--+ | | | | C +-+ | r |
| | | +-+ |D | E | | | | +---+1 | f |
| | | | +-+ |E| |a | N | | | | 0+---+ | a |
+----+---+---+ | | |L| |P| |t | R | | | | +-+-+ | | c |
| Gate Array | | +->|A+-ADDR->|R+-+a | E | +---|--|->| C | |<------------->| e |
| |<-+ | |T| |O| | G | |--|->| I | | | |
| DMA/ | | +-+ |M| +-+--+ | | | O +-+ | |
| Peripheral |<----+ (Note 1) +-+ | (Note 3) | | +---+ | |
| Interface | +-------------|--|----------------------->| |
| (DMAPIC) +-------DUSCC Control----------------------------+--|----------------------->| |
| | V | |
| |<--------DRQ0-DRQ15--------------------------------+-----------DRQ8-DRQ15---+ |
+------------+ | |
+---------+
Notes:
1. LAT is an abbreviation for Address Latch.
2. The Bus Master interface exists only on the Portmaster Adapter/A card; this gate
array is named the Shared Storage Interface on the Multiport Adapter, Model II card.
3. ENREG is an abbreviation for Enables Register.
Figure 2. IB Interface
+-------------+ | |<-------------------------- 8 DMA Channel Requests | | | | | |<-------------------------> Interrupt Requests and Acknowledges | | | | | | | +--------------------------> Data and Modem Controls | I | for 4 Adapter Card Ports | B | | | | I +--------------------------> 80C186 Control Signals | n | | t +--------------------------> System Clocks | e | | r +--------------------------> IB Chip Selects | f | | a | | c |<-------------------------> CIO Ports | e | | +--------------------------> CIO Control Signals | | | | | +--------------------------> Enables Register Outputs | | | | | |<-------------------------> Address/Data (8:15) | | | |<-------------------------> Buffered Address/Data (0:7) +-------------+
With two additional DUSCC chips on an IB, the co-processor adapter card can support up to eight ports, running full duplex at a data rate of 64K baud. A single port can be operated full duplex at a data rate of up to 2.048M baud for the Portmaster Adapter/A, and up to 1.544M baud for the Multiport Adapter, Model II.
The two DUSCCs on the co-processor adapter card support various communication protocols, both synchronous and asynchronous. Clocks for serial communication can be sourced externally by a modem, or alternately, the DUSCC can supply a clock for various communication speeds. For additional information, refer to "Dual Universal Serial Communications Controllers (DUSCC0 & 1)".
The performance of the DMA channels is more accurately described in the context of the line speeds that are supported. This discussion focuses on the limits of the DMA hardware, and what affect these limits have on the bandwidth of the 80C186. No statement is made concerning the software implication on bandwidth.
Note: List chaining and link list chaining limit performance by consuming bus bandwidth without moving data or executing 80C186 cycles. Therefore, the frequency of chaining must be considered; that is, short frames cause more frequent chaining operations.
The structure of the DMA arbiter logic ensures that at supported data rates, the 80C186 is able to perform, on average, one cycle for every cycle the DMA has control of the local bus.
On average, an 80C186 cycle is one wait state, or five clocks. Also, every I/O cycle is fixed at three wait states. Lastly, it takes three idle clocks for the DMA cycle to start after the local bus is granted to the DMA controller.
Since the clock frequency of the Multiport Adapter, Model II card is different than that of the Portmaster Adapter/A card, two separate calculations are provided.
Local bus utilization for the Multiport Adapter, Model II is shown in Figure 3.
Figure 3. Local Bus Utilization for Multiport Adapter, Model II
+---------------------+-----------+---------------------+-----------+-- - - - | 80C186 memory cycle | DMA cycle | 80C186 memory cycle | DMA cycle | | 5 clocks | 15 clocks | 5 clocks | 15 clocks | Etc | 500 ns | 1500 ns | 500 ns | 1500 ns | +---------------------+-----------+---------------------+-----------+-- - - -An 80C186 clock cycle is 100 ns at 10.0 MHz. A DMA cycle is possible every 500 ns + 1500 ns = 2000 ns. Each DMA cycle moves one byte, or eight bits off the line. Therefore, 1/2000 ns = 500 kilobytes/second are movable from the DUSCC chip to memory, or visa versa.
This is equivalent to a 4.0 megabits/second aggregate data rate for all channels. At this rate, the 80C186 is executing every 5 of 20 clocks, or 25% of the total bus utilization. The DMA owns 75% of the bus utilization.
To support eight full-duplex lines at 64 kilobits/second, an aggregate data rate of 128 kilobytes/second is required. This equals one byte every 8 us; or, equivalently, the DMA usage is 15 of 100 clocks, or 15%.
Applying this calculation to a 1.544 megabits/second, full-duplex data rate yields a DMA utilization of 58%, meaning the 80C186 is only processing 42% of its possible time. So, with one channel running at 1.544 megabits/second, full-duplex, the effective clock rate of the 80C186 is 4.2 MHz.
Local bus utilization for the Portmaster Adapter/A is shown in Figure 4.
Figure 4. Local Bus Utilization for Portmaster Adapter/A
+---------------------+-----------+---------------------+-----------+-- - - - | 80C186 memory cycle | DMA cycle | 80C186 memory cycle | DMA cycle | | 5 clocks | 15 clocks | 5 clocks | 15 clocks | Etc | 400 ns | 1200 ns | 400 ns | 1200 ns | +---------------------+-----------+---------------------+-----------+-- - - -An 80C186 clock cycle is 80 ns at 12.5 MHz. A DMA cycle is possible every 400 ns + 1200 ns = 1600 ns. Each DMA cycle moves one byte, or eight bits off the line. Therefore, 1/1600 ns = 625 kilobytes/second are movable from the DUSCC chip to memory, or visa versa.
This is equivalent to a 5.0 megabits/second aggregate data rate for all channels. At this rate, the 80C186 is executing every 5 of 20 clocks, or 25% of the total bus utilization. The DMA owns 75% of the bus utilization.
To support eight full-duplex lines at 64 kilobits/second, an aggregate data rate of 128 kilobytes/second is required. This equals one byte every 8 us; or, equivalently, the DMA usage is 15 of 100 clocks, or 15%.
Applying this calculation to a 2.048 megabits/second, full-duplex data rate yields a DMA utilization of 65%, meaning the 80C186 is only processing 35% of its possible time. So, with one channel running at 2.048 megabits/second, full-duplex, the effective clock rate of the 80C186 is 4.3 MHz.
As mentioned previously in Chapter 1. "System Overview", the co-processor adapter has two DUSCC chips, two CIO chips, and other hardware and software features that dictate the use of various devices on the Interface Board. This section describes the architecture of the co-processor adapter card that directly relates to the interface of the co-processor adapter and the Interface Board.
Memory/IO maps have been provided to illustrate the address partitions of both the co-processor adapter components and the IB address ranges.
Also covered in this section are some of the components that are needed for all Interface Boards; these include an Interface Board PROM or ID, and IB interface connectors.
Figure 5 shows the memory maps for the DRAM/PROM area and the I/O area of the co-processor adapter.
Figure 5. DRAM/PROM Memory Map
Co-Processor Adapter Co-Processor Adapter
DRAM/PROM Memory Map I/O Memory Map
Address Absolute Address Incremental
(Hex) Bytes (Hex) Bytes
---------+------------------+------- ---------+------------------+-------
1FFFFFh | | 2048K FFFFh | Reserved | 256
| Bank-switched | | |
| DRAM | FF00h | (-IO CS Active) |
| | ---------+------------------+-------
| | FEFFh | Interface Board | 3840
| | | I/O Space |
100000h | | F000h | (-IO CS Active) |
---------+------------------+------- ---------+------------------+-------
FFFFFh | Usable PROM | 1024K EFFFh | Interface Board | 4096
| (32KB) | | PROM Space |
F8000h | | E000h |(-ROS CS Active) |
---------+------------------+------- ---------+------------------+-------
F7FFFh | Reserved | 992K 1BFFh | DUSCC 3 Area | 256
| (32KB) | | Interface Board |
F0000h | | 1B00h | (-SCC3 CS Active)|
---------+------------------+------- ---------+------------------+-------
EFFFFh | | 960K 1AFFh | DUSCC 2 Area | 256
| DRAM | | Interface Board |
| | 1A00h | (-SCC2 CS Active)|
| | ---------+------------------+-------
| | 19FFh | DUSCC 0 & 1 | 512
| | | Adapter Card |
| | 1800h | |
| | ---------+------------------+-------
| | 17FFh . . 4094
| | . Adapter Card .
| | 0802h . .
00000h | | ---------+------------------+--------
---------+------------------+------- 0800h | Enables Register | 2
---------+------------------+--------
05FFh | CIO 0 & 1 | 1152
| Adapter Card |
Note: The Multiport Adapter, Model II 0180h | |
card has a maximum of 1MB of DRAM. ---------+------------------+--------
017Fh | | 384
| Adapter Card |
| |
0000h | |
---------+------------------+--------
The Signetics SCN26562 Dual Universal Serial Communications Controller (DUSCC) chip is used by the co-processor adapter for data communications. Up to four of these chips are supported by one co-processor adapter. Two of the DUSCCs (0 and 1) reside on the co-processor adapter, and up to two more DUSCCs (2 and 3) can reside on the Interface Board. This provides the co-processor adapter with up to eight individually programmable ports for serial communications functions.
After initial configuring of the DUSCCs by the Realtime Control Microcode, a major portion of the serial communications workload is off-loaded from the 80C186 processor and is performed by the DUSCCs. (Refer to the appropriate Signetics publication for a detailed description of the SCN26562 DUSCC.)
The DUSCCs provide many versatile features, such as:
The DUSCC chip is programmed to satisfy special serial communications requirements and to support standard communications protocols. Each communications port has a transmitter section and a receiver section, and may be run in a full-duplex or a half-duplex mode of operation.
The DUSCCs provide controller logic for each of the data communications ports on the co-processor adapter. The DUSCC interfaces with the following components on the co-processor adapter:
The block diagram shown in Figure 1 provides an overview of the interconnections.
Each of the DUSCCs uses a single +5 volt power supply.
The DUSCC pin functions are shown in Figure 6.
PORT A
+-------------------------+ ------
+ <-->| D7 TxDA |---> + Serial data
| <-->| D6 RxDA |<--- +
| <-->| D5 |
| <-->| D4 TRxCA |<--> + Port clocks
Data bus | <-->| D3 RTxCA |<--> +
| <-->| D2 |
| <-->| D1 -RTSAN/SYNOUTIAN|---> + Port controls
+ <-->| D0 -CTSAN |<--- | for modem, DMA,
| -DCDDAN/SYNIAN|<--- + or other
+ --->| A6 |
| --->| A5 |
Address | --->| A4 | PORT B
bus | --->| A3 | ------
| --->| A2 TxDB |---> + Serial data
+ --->| A1 RxDB |<--- +
| |
+ --->| -WRN TRxCB |<--> + Port clocks
80C186 | --->| -RDN RTxCB |<--> +
Bus timing | | -RDYN |
control | --->| -CEN -RTSBN/SYNOUTIBN|---> + Port controls
and reset + --->| -RESETN -CTSBN |<--- | for modem, DMA,
| -DCDDBN/SYNIBN|<--- + or other
| |
+ <---| -IRQN |
Interrupt + --->| -IACKN |
| |
+ --->| -RTxDAKAN/GPI1AN |
| --->| -RTxDAKBN/GPI1BN |
| --->| -TxDAKAN/GPI2AN |
DMA | --->| -TxDAKBN/GPI2BN |
interface | <---| -RTxDRQAN/GPO1AN |
| <---| -RTxDRQBN/GPO1BN |
| <---| -TxDRQAN/GPO2AN |
| <---| -TxDRQBN/GPO2BN |
+ <-->| -EOPN |
| X2 X1/CLK|
+-------------------------+
^ ^ ^
+5V GND PCLK
All of the possible functions and features available with the DUSCC registers are not usable on the co-processor adapter. The known programming restrictions of the DUSCC chip for the co-processor adapter are described on the following pages. Failure to comply with these restrictions will lead to unpredictable results.
Bit 5 Bit 4 Bit 3 ----- ----- ----- 0 1 1 : Full-duplex, dual-address 1 1 1 : Polled or interruptThese are the only two valid bit combinations for bits 5 through 3 of CMR2. Use 011 for DMA mode operation, or 111 for polled or interrupt mode operation.
A channel cannot be dynamically reconfigured. Observe the following rules during write operations:
Do Not Write To Condition --------------- ------------------------------ CMR1, CMR2, S1R, When the channel is in use S2R, or PCR (receiver or transmitter enabled) RPR or RTR When the receiver is enabled TPR or TTR When the transmitter is enabled CTCR, CTPRH, or When the counter/timer is enabled CTPRLThe Realtime Control Microcode, along with PROM Services and Realtime Interface Co-Processor Extended Services, is designed to manage the programming of the DUSCC. However, the user may want to program the DUSCC directly to obtain certain performance improvements.
The DUSCC has an operating frequency of 14.7456 MHz to support most serial communication line speeds to 0.01% tolerance. The co-processor adapter supports DUSCC data rates up to 1.544M bits-per-second for the Multiport Adapter, Model II, and up to 2.048M bits-per-second for the Portmaster Adapter/A. To support either data rate, a clock of the appropriate speed must be supplied to the DUSCC, typically from a high-speed modem. The DUSCC, with no externally supplied clock, can support synchronous rates up to 230.4K bits-per-second full duplex, using the digital phase-locked loop (DPLL), as shown in Figure 7. Also, the DUSCC can support asynchronous data rates up to 115.2K bits-per-second full duplex. Figure 7 details the data rates that can be achieved with the DUSCC.
Figure 7. DUSCC Clocking Rates Supported by Co-Processor Adapter
+----------+----------------+------------------+--------+--------+ | Rate | TXCLK Source | RXCLK Source | Half | Full | | (Kb/sec) | Sync Async | Sync Async | Duplex | Duplex | +----------+-------+--------+---------+--------+--------+--------+ | 0-2048 | E | - | E | - | Yes | Yes | | 0-1544 | E | - | E | - | Yes | Yes | | 230.4 | C | - | DX | - | Yes | Yes | | 115.2 | - | R | - | R | Yes | Yes | | 76.8 | - | R | - | R | Yes | Yes | | 57.6 | C | C | DC | C | Yes | Yes | | 38.4 | C, B | C, B | DC, DB | C, B | Yes | Yes | | 28.8 | C | C | DC | C | Yes | Yes | | 19.2 | C, B | C, B | DC, DB | C, B | Yes | Yes | | 14.4 | C | C | DC | C | Yes | Yes | | 9.6 | C, B | C, B | DC, DB | C, B | Yes | Yes | +----------+-------+--------+---------+--------+--------+--------+Legend
E = Externally supplied clock
C = Counter/Timer (internal to DUSCC)
B = Bit Rate Generator (internal to DUSCC)
DX = Digital Phase Locked Loop (DPLL) ; the clock to drive the DPPL is
supplied from the X1/CLK input pin.
DC = Digital Phase Locked Loop (DPLL) ; the clock to drive the DPPL is
supplied from the Counter/Timer.
DB = Digital Phase Locked Loop (DPLL) ; the clock to drive the DPPL is
supplied from the bit rate generator.
R = RTxC pin; requires the output from the Counter/Timer to be output
on the TRxC pin and externally jumpered back to the RTxC pin.
Rates lower than those shown in
Figure 7
are also possible using either
the Counter/Timer or Bit Rate Generator.
Refer to the Signetics SCN26562 Product Specification for details.
The base addresses of the DUSCCs are listed in Figure 8.
Figure 8. DUSCC Base Addresses
+------------+-------------+--------------------------+ | Device | Address | Comments | | | (hex) | | +------------+-------------+--------------------------+ | DUSCC0 | 1800 | Supports ports 0 and 1 | | DUSCC1 | 1900 | Supports ports 2 and 3 | +------------+-------------+--------------------------+Multiple registers are used for each DUSCC channel that is programmed by the co-processor adapter to configure the functional personality of the channels. Direct addressing is used for all the data and control registers associated with the DUSCC. The co-processor adapter issues a series of commands to initialize the desired mode of operation. The final action is to set the receiver or transmitter enable.
Some of the program selectable options for configuring the DUSCC functional personality are as follows:
Figure 9. Channel Mode Configuration and Pin Description Registers
+----------+--------+--------+--------+------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+------------------------------+ | CMR1 | 00 | 40 | R/W | Channel Mode Register 1 | | CMR2 | 02 | 42 | R/W | Channel Mode Register 2 | | S1R | 04 | 44 | R/W | SYN1/Secondary Address 1 Reg | | S2R | 06 | 46 | R/W | SYN2/Secondary Address 2 Reg | | PCR | 1C | 5C | R/W | Pin Configuration Register | +----------+--------+--------+--------+------------------------------+Figure 10. Transmitter and Receiver Parameter and Timing Registers
+----------+--------+--------+--------+--------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+--------------------------------+ | TPR | 08 | 48 | R/W | Transmitter Parameter Register | | TTR | 0A | 4A | R/W | Transmitter Timing Register | | RPR | 0C | 4C | R/W | Receiver Parameter Register | | RTR | 0E | 4E | R/W | Receiver Timing Register | | OMR | 16 | 56 | R/W | Output & Misc. Register | | TXFIFO | 20 | 60 | W | Transmitter FIFO | | RXFIFO | 28 | 68 | R | Receiver FIFO | +----------+--------+--------+--------+--------------------------------+Figure 11. Counter/Timer Control and Value Registers
+----------+--------+--------+--------+-------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+-------------------------------+ | CTPRH | 10 | 50 | R/W | Counter/Timer Preset Reg High | | CTPRL | 12 | 52 | R/W | Counter/Timer Preset Reg Low | | CTCR | 14 | 54 | R/W | Counter/Timer Control Reg | | CTH | 18 | 58 | R | Counter/Timer High | | CTL | 1A | 5A | R | Counter/Timer Low | +----------+--------+--------+--------+-------------------------------+Figure 12. Interrupt Control and Status Registers
+----------+--------+--------+--------+------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+------------------------------+ | RSR | 30 | 70 | R/W | Receiver Status Register | | TRSR | 32 | 72 | R/W | Trans/Rec Status Register | | ICTSR | 34 | 74 | R/W | Input & C/T Status Register | | GSR* | 36 | 36 | R/W | General Status Register | | IER | 38 | 78 | R/W | Interrupt Enable Register | | (IVR) | 3C | | R/W | Interrupt Vector Reg (unmod) | | (IVRM) | 7C | | R | Interrupt Vector Reg (mod) | | (ICR) | 3E | | R/W | Interrupt Control Register | +----------+--------+--------+--------+------------------------------+ | Note: Registers with the symbol (*) are shared between ports | | A and B. Registers in parentheses ( ) are not port-specific.| --------------------------------------------------------------------Figure 13. Command Registers
+----------+--------+--------+--------+--------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+--------------------------+ | CCR | 1E | 5E | R/W | Channel Command Register | | MRR | 7E | | R/W | Master Reset Register | +----------+--------+--------+--------+--------------------------+
Four other communication signals are handled through the CIO. These are detailed in the "Counter/Timer and Parallel I/O Units (CIO0 & 1)".
The DMA/peripheral interface chip acts as the interrupt arbiter for all DUSCC0-3 and CIO0-1 interrupts. The DMA/peripheral interface chip contains six command ports that are used to re-enable interrupts within the chip for the 80C186 that may be pending from any DUSCC or CIO.
During the interrupt subroutine, the user must do a byte I/O write to the appropriate command port to re-enable interrupts from that particular DUSCC or CIO device. The data is don't care. The I/O write to the particular DMAEOI command port must be at least two instructions after the write to the appropriate DUSCC status register that clears the interrupt. Both writes must be before the 80C186 EOI is issued.
The addresses for the particular DMAEOI command ports are as follows:
Figure 14. DMAEOI Command Port Addresses
+---------------+------------+ | Particular | Address | | DMAEOI | (hex) | +---------------+------------+ | DUSCC0 EOI | 3220 | | DUSCC1 EOI | 3221 | | CIO0 EOI | 3224 | | CIO1 EOI | 3225 | +---------------+------------+
Diagnostics are provided for the DUSCC. For diagnostic testing, the DUSCC is run in an internal data wrap mode, at various baud rates and bit modes. The DUSCC test routine is called by the power-on self-test (POST) and is callable by the user.
The 8036 Counter/Timer and Parallel I/O Unit provides peripheral I/O support for the co-processor adapter. The co-processor adapter contains two CIO chips (CIO0 and 1). Features of each CIO are:
One timer and one 4-bit I/O port are used by the on-board watchdog timer to provide interrupt notification of a runaway CPU; the second 4-bit I/O port is accessible at connector K2 which attaches to the Interface Board.
Two 8-bit ports on each CIO (32 total bits) are used for peripheral I/O control of data through the co-processor adapter's Interface Boards. These 32 bits can provide eight serial ports with four more control lines than are provided by the DUSCC. The naming convention of these control lines becomes important when implementing the Interface Board ROS. The additional control lines are:
Any of the input bits (DSR, RI, or HRS) can be programmed to generate an interrupt on a change of state.
Five timers are available for application tasks running on the co-processor adapter.
Additional features include firmware support for CIO diagnostic routines, and user interfaces for performing PROM Services.
Figure 15 shows the pin functions for the 8036 CIO.
+----------------+
+ <-->| AD7 PA7 |<--> +
| <-->| AD6 PA6 |<--> |
Address/ | <-->| AD5 PA5 |<--> |
data bus | <-->| AD4 PA4 |<--> | Port A
| <-->| AD3 PA3 |<--> |
| <-->| AD2 PA2 |<--> |
| <-->| AD1 PA1 |<--> |
+ <-->| AD0 PA0 |<--> +
| |
Bus timing + --->| AS PC3 |<--> +
and reset + --->| DS PC2 |<--> | Port C
| | |
+ --->| R/W PC1 |<--> |
Control | --->| CS1 PC0 |<--> +
| | |
+ --->| CS0 PB7 |<--> +
| | |
+ <---| INT PB6 |<--> |
| --->| INTACK PB5 |<--> |
Interrupt | --->| IEI PB4 |<--> | Port B
+ <---| IEO PB3 |<--> |
| PB2 |<--> |
| PB1 |<--> |
| PB0 |<--> +
+----------------+
^ ^ ^
+5V GND PCLK
One port and one timer of CIO0 are used by the watchdog timer to provide interrupt notification of a runaway CPU. The remaining ports on the two CIOs are either used as modem controls for the serial ports or they are available for general-purpose I/O with custom Interface Boards. The remaining five timers are allocated to the user for application-specific requirements. The following tables show the bit assignments for CIO0 and CIO1. The naming convention of these two bits becomes important when implementing the Interface Board ROS.
CIO0 Bit Assignments
+--------+----------+ +--------+----------+
| Port A | Signal | | Port B | Signal |
| Bit | Name | | Bit | Name |
+--------+----------+ +--------+----------+
| PA0 | DTR0 | | PB0 | DSR0 |
| PA1 | DTR1 | | PB1 | DSR1 |
| PA2 | DTR2 | | PB2 | DSR2 |
| PA3 | DTR3 | | PB3 | DSR3 |
| PA4 | DTR4 | | PB4 | DSR4 |
| PA5 | DTR5 | | PB5 | DSR5 |
| PA6 | DTR6 | | PB6 | DSR6 |
| PA7 | DTR7 | | PB7 | DSR7 |
+--------+----------+ +--------+----------+
CIO1 Bit Assignments
+--------+----------+ +--------+----------+
| Port A | Signal | | Port B | Signal |
| Bit | Name | | Bit | Name |
+--------+----------+ +--------+----------+
| PA0 | RI0 | | PB0 | HRS0 |
| PA1 | RI1 | | PB1 | HRS1 |
| PA2 | RI2 | | PB2 | HRS2 |
| PA3 | RI3 | | PB3 | HRS3 |
| PA4 | RI4 | | PB4 | HRS4 |
| PA5 | RI5 | | PB5 | HRS5 |
| PA6 | RI6 | | PB6 | HRS6 |
| PA7 | RI7 | | PB7 | HRS7 |
+--------+----------+ +--------+----------+
Refer to
"Watchdog Timer" for Port C pin assignments.
The CIO peripheral clock (PCLK) has an operating frequency of 3.6864 MHz.
The watchdog timer (timer 3) operates at a frequency of 763 Hz (T3CLK). It has a range from 1.31 milliseconds to 86 seconds, in increments of 1.31 milliseconds. Refer to "Watchdog Timer".
Refer to the appropriate Zilog publication for a detailed description of the 8036 Counter/Timer and Parallel I/O Unit.
Programming the CIO is accomplished by loading the CIO control registers with the proper bits to implement the desired operation modes. CIO counters/timers are treated as separate devices from the CIO ports. This allows greater flexibility in assigning timer resources. The timers can be driven from PCLK which is 3.6864 Mhz. Some of the 8036 CIO features are not utilized by the co-processor adapter. These include the handshaking mode and its various options (de-skew and so forth).
The base addresses of the CIOs are:
CIO0: 0180h CIO1: 0500hThe CIO operates in left-shift mode. When performing I/O operations to the CIO, subsequent I/O operations must be separated by at least two CPU cycles. A good instruction to use is JMP $+2. This is required because the 80C186 can process I/O operations faster than the CIO can handle them. Bit definitions for each register are in the Zilog Technical Reference.
The addresses of individual registers are as shown below in the tables named:
The main control registers are dedicated for co-processor adapter use only, and should not be directly written to by applications. Support for application tasks is provided by PROM Services.
+--------+--------+-----------------------------------------------+ | Offset | Access | Function | +--------+--------+-----------------------------------------------+ | 0000h | R/W | Master interrupt control register | | | | | | 0002h | R/W | Master configuration control register. | | | | Bit 4 is dedicated to the watchdog timer | | | | and should not be programmed. | | | | Bit 3 (=0) allows ports A and B to operate | | | | independently and should not be changed. | | | | | | 0004h | R/W | Port A interrupt vector | | | | | | 0006h | R/W | Port B interrupt vector | | | | | | 0008h | R/W | Counter/timer interrupt vector | | | | | | 000Ah | R/W | Port C data path polarity register. | | | | (Reserved for co-processor adapter use only.) | | | | | | 000Ch | R/W | Port C data direction register. | | | | (Reserved for co-processor adapter use only.) | | | | | | 000Eh | R/W | Port C special I/O control register. | | | | (Reserved for co-processor adapter use only.) | +--------+--------+-----------------------------------------------+
+--------+--------+-----------------------------------------------+ | Offset | Access | Function | +--------+--------+-----------------------------------------------+ | 0010h | R/W | Port A command and status. | | | | Bits 2 - 3 do not apply in the bit port mode. | | | | | | 0012h | R/W | Port B command and status. | | | | Bits 2 - 3 do not apply in the bit port mode. | | | | | | 0014h | R/W | Counter/timer 1 command and status | | | | | | 0016h | R/W | Counter/timer 2 command and status | | | | | | 0018h | R/W | Counter/timer 3 command and status. | | | | (Reserved for co-processor adapter use only.) | | | | | | 001Ah | R/W | Port A data register | | | | | | 001Ch | R/W | Port B data register | | | | | | 001Eh | R/W | Port C data register. | | | | (Reserved for co-processor adapter use only.) | +--------+--------+-----------------------------------------------+
+--------+--------+-----------------------------------------------+ | Offset | Access | Function | +--------+--------+-----------------------------------------------+ | 0020h | R | Counter/timer 1 current count MSB | | | | | | 0022h | R | Counter/timer 1 current count LSB | | | | | | 0024h | R | Counter/timer 2 current count MSB | | | | | | 0026h | R | Counter/timer 2 current count LSB | | | | | | 0028h | R | Counter/timer 3 current count MSB | | | | | | 002Ah | R | Counter/timer 3 current count LSB | | | | | | 002Ch | R/W | Counter/timer 1 time constant MSB | | | | | | 002Eh | R/W | Counter/timer 1 time constant LSB | | | | | | 0030h | R/W | Counter/timer 2 time constant MSB | | | | | | 0032h | R/W | Counter/timer 2 time constant MSB | | | | | | 0034h | R/W | Counter/timer 3 time constant MSB. | | | | (Reserved for co-processor adapter use only.) | | | | | | 0036h | R/W | Counter/timer 3 time constant LSB. | | | | (Reserved for co-processor adapter use only.) | | | | | | 0038h | R/W | Counter/timer 1 mode specification | | | | | | 003Ah | R/W | Counter/timer 2 mode specification | | | | | | 003Ch | R/W | Counter/timer 3 mode specification. | | | | (Reserved for co-processor adapter use only.) | | | | | | 003Eh | R/W | Current vector | +--------+--------+-----------------------------------------------+ Note: MSB = Most significant byte LSB = Least significant byte
+--------+--------+-----------------------------------------------+ | Offset | Access | Function | +--------+--------+-----------------------------------------------+ | 00040h | R/W | Port A mode specification. | | | | Bits 3 - 7 must be 0s to keep the port | | | | specified as in bit port mode. | | | | The de-skew timer function is not supported. | | | | Therefore, bit 0 is for latch on pattern | | | | match. | | | | | | 00042h | R/W | Port A handshake specification. | | | | Register is always zero since handshaking | | | | is not utilized. | | | | | | 00044h | R/W | Port A data path polarity | | | | | | 00046h | R/W | Port A data direction | | | | | | 00048h | R/W | Port A special I/O control | | | | | | 0004Ah | R/W | Port A pattern polarity | | | | | | 0004Ch | R/W | Port A pattern transition | | | | | | 0004Eh | R/W | Port A pattern mask (which bits to test) | +--------+--------+-----------------------------------------------+
+--------+--------+-----------------------------------------------+ | Offset | Access | Function | +--------+--------+-----------------------------------------------+ | 00050h | R/W | Port B mode specification. | | | | Bits 3 - 7 must be 0s to keep the port | | | | specified as in bit port mode. | | | | The de-skew timer function is not supported. | | | | Therefore, bit 0 is for latch on pattern | | | | match. | | | | | | 00052h | R/W | Port B handshake specification. | | | | Register is always zero since handshaking | | | | is not utilized. | | | | | | 00054h | R/W | Port B data path polarity | | | | | | 00056h | R/W | Port B data direction | | | | | | 00058h | R/W | Port B special I/O control | | | | | | 0005Ah | R/W | Port B pattern polarity | | | | | | 0005Ch | R/W | Port B pattern transition | | | | | | 0005Eh | R/W | Port B pattern mask (which bits to test) | +--------+--------+-----------------------------------------------+
As a preventive device, a watchdog timer has been incorporated on the co-processor adapter card. This timer, once activated, must continually be strobed by software so that it will not time out. If the 80C186 processor ever has a fatal error, this timer will reach its terminal count. The terminal count will:
The watchdog timer operates at a frequency of 763 Hz (T3CLK). It has a range from 1.31 milliseconds to 86 seconds, with a step size of 1.31 milliseconds.
The watchdog timer is timer 3 in CIO0. The table below shows that if the watchdog timer is never initialized, the LED will stay on. The user can directly control the LED by clearing PC2, or allowing it to be controlled by the watchdog timer.
+--------+-----+--------+--------------------------------+ | CIO0 | | | | | Port C | Pin | Signal | Description | +--------+-----+--------+--------------------------------+ | PC0 | 21 | WDOG | Timer 3 output, Watchdog Timer | | PC1 | 22 | T3CLK | Timer 3 clock input, 763 Hz | | PC2 | 23 | WD CNTL| Watchdog LED control | | PC3 | 24 | RSVD | Reserved | +--------+-----+--------+--------------------------------+ +-----------+--------+ | CIO0 | | | Port C | LED | +-----+-----+ Status | | PC2 | PC0 | | +-----+-----+--------+ | 0 | 0 | On | | 0 | 1 | On | | 1 | 0 | Off | | 1 | 1 | On | +-----+-----+--------+
The signal flow of the IB is such that the TTL or logic-level signals flow to, and from, the co-processor adapter card and the IB through three straight-pin connectors (K0, K1, and K2). These connectors (150 pins total) carry the signals, power, and ground to the Interface Board. It is extremely important that an Interface Board use the mating male connector that properly fits the female connectors of the co-processor adapter card. The part numbers for these connectors are listed in Chapter 6. "Mechanical Hardware".
The external communication signals travel through a D-shell connector on the Interface Board. Information regarding this connector can be found in Chapter 6. "Mechanical Hardware".
Wrap plugs are often used as a diagnostic tool to isolate problems with the external communication signals. The wrap plug connects the output signals of the external communication connector directly to the inputs of the connector. This allows communication from driver to receiver, however, it does not simulate any line loading that may occur in an actual application.
Figure 16 shows the signal-to-pin assignments of the three co-processor adapter connectors (K0, K1, and K2) that connect to the Interface Board. The organization of the pins shown on these connector symbols differs from the physical organization of pins on the actual connector. Refer to Chapter 6. "Mechanical Hardware" for actual connector pin locations.
Figure 16. Interface Board Connector Diagram
IB CONNECTORS
K0 K1 K2
+---+ +-------+ +-------+
-TXREQ4 1| | BAD0 1| |31 -RTS2 -RDID06 1| |31 -DUSCC RD
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-RXREQ4 2| | -12V 2| |32 -CTS2 -SCC3 INT REQ2| |32 7.3MHz
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 3| | BAD1 3| |33 -DCD2 GND 3| |33 DTE/DCECLK1
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 4| | BAD2 4| |34 RXCLK2 DBSRDY 4| |34-SCC2 INT REQ
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-TXREQ5 5| | BAD3 5| |35 TXCLK2 DTE/DCECLK0 5| |35 -SCC2 INTACK
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-RXREQ5 6| | BAD4 6| |36 -DTR1 +5V 6| |36 GND
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 7| | BAD5 7| |37 TXD3 -DTR0 7| |37 ZILOG R/-W
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 8| | BAD6 8| |38 RXD3 -SCC3 INTACK 8| |38 -DUSCC WR
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 9| | +12V 9| |39 -RTS3 GND 9| |39 14.7MHz
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-TXREQ6 10| | BAD7 10| |40 -CTS3 -DTR2 10| |40 N/C
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-RXREQ6 11| | -SCC2 CS 11| |41 -DCD3 -ROS CS 11| |41 -AS
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 12| | -SCC3 CS 12| |42 RXCLK3 +5V 12| |42 GND
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 13| | TXD0 13| |43 TXCLK3 -DTR4 13| |43 -ZILOG DS
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-TXREQ7 14| | RXT0 14| |44 -DTR3 -DTR5 14| |44 DTE/DCECLK2
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-RXREQ7 15| | -RTS0 15| |45 -R10 GND 15| |45 DTE/DCECLK3
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 16| | -12V 16| |46 -R11 -DTR6 16| |46 -DSR1
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 17| | -CTS0 17| |47 -R12 -DTR7 17| |47 -DSR3
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
N/C 18| | -DCD0 18| |48 -R13 +5V 18| |48 GND
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-RD 19| | RXCLK0 19| |49 -R14 -DSR0 19| |49 PC01
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-WR 20| | TXCLK0 20| |50 -R15 -IO CS 20| |50 PC11
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
AD8 21| | TXD1 21| |51 -R16 -GND 21| |51 DTE/DCECLK4
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
AD9 22| | RXD1 22| |52 -R17 -DSR2 22| |52 DTE/DCECLK5
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
AD10 23| | +12V 23| |53 -HRS0 -LBRES 23| |53 EALE
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-EOPN 24| | -RTS1 24| |54 -HRS1 +5V 24| |54 GND
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-AD11 25| | -CTS1 25| |55 -HRS2 -DSR4 25| |55 CLK0
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-AD12 26| | -DCD1 26| |56 -HRS3 -DSR5 26| |56 DTE/DCECLK6
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-AD13 27| | RXCLK1 27| |57 -HRS4 GND 27| |57 DTE/DCECLK7
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-AD14 28| | TXCLK1 28| |58 -HRS5 -DSR6 28| |58 PC21
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-AD15 29| | TXD2 29| |59 -HRS6 -DSR7 29| |59 PC31
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
-BHE 30| | RXD2 30| |60 -HRS7 +5V 30| |60 GND
--------------+-o | --------------+-o o-+-------------- --------------+-o o-+---------------
+---+ +-------+ +-------+
K0 K1 K2
Figure 17 alphabetically lists the functional pin assignments for the three Interface Board connectors (K0, K1, and K2). Note that the signal direction in the column labelled Type is referenced from the co-processor adapter card.
Figure 17. Functional Pin Assignments of Interface Board
+----------------+-----------+--------+-----+-------------------------------------------------+
| Mnemonic | Connector | Pin |Type | Name and Function |
+----------------+-----------+--------+-----+-------------------------------------------------+
| | | | | |
| AD(8:15) | K0 | 21-23, | I/O | Unbuffered high-order byte of the 80C186 |
| | | 25-29 | | multiplexed address and data bus. |
| | | | | |
| -AS | K2 | 41 | O | Address Strobe: a CIO input that latches the |
| | | | | -INTACK or -CS0 signals in the CIO. |
| | | | | |
| BAD(0:7) | K1 | 1,3-8, | I/O | Buffered low-order byte of 80C186 multiplexed |
| | | 10 | | address and data bus. The DMAPIC gate array |
| | | | | controls the direction of this for DMAPIC- |
| | | | | specific decodes only. |
| | | | | |
| -BHE | K0 | 30 | O | Bus High Enable: an 80C186 signal that indi- |
| | | | | cates data is being transferred on high-order |
| | | | | byte AD8-AD15. |
| | | | | |
| CLKO | K2 | 55 | O | Clockout: the clockout signal from the 80C186. |
| | | | | The clock frequency is 12.5 MHz for Portmaster |
| | | | | and 10MHz for Multiport, Model II. |
| | | | | |
| -CTS(0:3) | K1 | 17,25, | I/O | Clear-to-Send Output or Loop Control Input: |
| | | 32,40 | | a DUSCC port-specific control signal. |
| | | | | When not in BOP Loop mode, this signal can be |
| | | | | programmed to act as an enable for the trans- |
| | | | | mitter. |
| | | | | |
| DBSRDY | K2 | 4 | I | Interface Board Synchronous Ready: allows an |
| | | | | Interface Board device to insert wait states on |
| | | | | I/O cycles to the Interface Board from the |
| | | | | 80C186 in the I/O CS range. |
| | | | | |
| -DCD(0:3) | K1 | 18,26, | I | Data Carrier Detect or External Sync Input: |
| | | 33,41 | | a DUSCC port-specific control signal. It can |
| | | | | be used as a DCD input to enable the receiver, |
| | | | | or as a general-purpose active-low input. |
| | | | | |
| -DSR(0:7) | K2 | 19,46 | I/O | CIO-0 Port B I/O Lines: eight bidirectional I/O|
| | | 22,47 | | lines that transfer information between the |
| | | 25,26 | | CIO's Port B and external devices. These lines |
| | | 28,29 | | may also be used to provide external access to |
| | | | | counters/timers 1 and 2. |
| | | | | |
| DTE/DCECLK(0:7)| K2 | 5,33, | O | Enables Register Outputs: eight general-purpose|
| | | 44,45, | | control lines driven by the co-processor card's |
| | | 51,52, | | Enables Register. |
| | | 56,57 | | |
| | | | | |
| -DTR(0:7) | K1 | 36,44 | I/O | CIO-0 Port A I/O Lines: eight bidirectional I/O|
| | K2 | 7,10, | | lines that transfer information between the |
| | | 13,14 | | CIO's Port A and external devices. |
| | | 16,17 | | |
| | | | | |
| -DUSCC RD | K2 | 31 | O | DUSCC Read Strobe: a DUSCC-specific signal used|
| | | | | in conjunction with -SCCX CS to read data from a|
| | | | | DUSCC module. |
| | | | | |
| -DUSCC WR | K2 | 38 | O | DUSCC Write Strobe: a DUSCC-specific signal |
| | | | | used in conjunction with -SCCX CS to write data |
| | | | | to a DUSCC module. |
| | | | | |
| EALE | K2 | 53 | O | Address Latch Enable: an active-high signal |
| | | | | that allows latching of 80C186 or DMAPIC |
| | | | | addresses. |
| | | | | |
| -EOPN | K0 | 24 | I/O | Done: a DUSCC-specific signal used during DMA |
| | | | | read and write operations. This signal is an |
| | | | | open drain/collector signal, and is pulled up |
| | | | | on the co-processor adapter card. |
| | | | | |
| -HRS(0:7) | K1 | 53-60 | I/O | CIO-1 Port B I/O Lines: eight bidirectional |
| | | | | I/O lines that transfer information between |
| | | | | the CIO's Port B and external devices. These |
| | | | | lines may also be used to provide external |
| | | | | access to counter/timers 1 and 2. |
| | | | | |
| -IO CS | K2 | 20 | O | Interface Board I/O Chip Select: an I/O chip |
| | | | | select decoded in the 80C186 I/O address range |
| | | | | from F000h-FFFFh. The 80C186 uses the addresses|
| | | | | from FF00h-FFFFh, therefore, all IBs using the |
| | | | | signal must block any decodes in this range. |
| | | | | |
| -LBRES | K2 | 23 | O | Reset: an active-low pulse generated on power- |
| | | | | up or by writing a CMDRESET to the COMREG on the|
| | | | | co-processor adapter card. This signal resets |
| | | | | the 80C186, and causes a partial reset of the |
| | | | | co-processor adapter card's RAM Controller and |
| | | | | Bus Master Interface. |
| | | | | |
| PC01,PC11 | K2 | 49,50 | I/O | CIO-1 PC(0:3): general-purpose signals for the |
| PC21,PC31 | | 58,59 | | I/O lines to CIO-1 Port C; also allow external |
| | | | | access to timer 3 of CIO-1. These signals are |
| | | | | open-drain drivers and require pullup resistors.|
| | | | | |
| -RD | K0 | 19 | O | Read: the 80C186 read data strobe signal. |
| | | | | This signal is also driven during DMAPIC DMA |
| | | | | cycles. |
| | | | | |
| -RDID86 | K2 | 1 | O | Interface Board ID Chip Select: an active-low |
| | | | | chip select decoding address 86h, the location |
| | | | | of the Interface Board ID. |
| | | | | |
| -RI(0:7) | K1 | 45-52 | I/O | CIO-1 Port A I/O Lines: eight bidirectional |
| | | | | I/O lines that transfer information between |
| | | | | the CIO's Port A and external devices. |
| | | | | |
| -ROS CS | K2 | 11 | O | IB ROS Chip Select: an active-low decode of |
| | | | | the 80C186 address range E000h-EFFFh. This is |
| | | | | the address range where the IB PROM is located. |
| | | | | |
| -RTS(0:3) | K1 | 15,24, | O | Request-to-Send or Sync Detect Output: a DUSCC |
| | | 31,39 | | port-specific output that can be used as a |
| | | | | request-to-send modem control signal, or as a |
| | | | | sync output. It can be asserted one bit time |
| | | | | after a specific character is detected by a |
| | | | | receiver. |
| | | | | |
| RXCLK(0:3) | K1 | 19,27, | I/O | Receiver/Transmitter Clock: a DUSCC port- |
| | | 34,42 | | specific signal. As an input, it can be pro- |
| | | | | grammed to supply the receiver, transmitter, |
| | | | | counter/timer, or DPLL clock. As an output, it |
| | | | | can supply the counter/timer output, the |
| | | | | transmitter shift clock (1X), or the receiver |
| | | | | sampling clock (1X). |
| | | | | |
| RXD(0:3) | K1 | 14,22, | I | Receiver Serial Data Input: a DUSCC port- |
| | | 30,38 | | specific input for data. |
| | | | | |
| -RXREQ(4:7) | K0 | 2,6,11,| I | DMA Channel Request: an active-low signal that |
| | | 15 | | is used to request service from one of four |
| | | | | user-definable DMA channels. |
| | | | | |
| -SCC2 CS | K1 | 11,12 | I | DUSCC 2 and DUSCC 3 Chip Selects: an active- |
| -SCC3 CS | | | | low decode signal for the 80C186 I/O address |
| | | | | ranges 1A00h-1AFFh, and 1B00h-1BFFh, respec- |
| | | | | tively. |
| | | | | |
| -SCC2 INT REQ | K2 | 34,2 | I | DUSCC 2 and 3 Interrupt Request: a signal that |
| -SCC3 INT REQ | | | | allows a device to interrupt the 80C186. The |
| | | | | device must be capable of supplying an interrupt|
| | | | | vector during an interrupt acknowledge cycle. |
| | | | | |
| -SCC2 INTACK | K2 | 35,8 | O | DUSCC 2 and 3 Interrupt Acknowledge: a signal |
| -SCC3 INTACK | | | | that allows a device to receive an acknowledge- |
| | | | | ment of its interrupt request and gate the |
| | | | | interrupt vector onto the bus. |
| | | | | |
| TXCLK(0:3) | K1 | 20,28, | I/O | Transmitter/Receiver Clock: a DUSCC port- |
| | | 35,43 | | specific I/O signal. As an input, it can |
| | | | | supply the receiver, transmitter, counter/timer,|
| | | | | or DPLL clock. As an output, it can supply the |
| | | | | counter/timer output, DPLL output, transmitter |
| | | | | clock, receiver clock, etc. |
| | | | | |
| TXD(0:3) | K1 | 13,21, | O | Transmitter Serial Data Output: a DUSCC port- |
| | | 29,37 | | specific output signal for data. |
| | | | | |
| -TXREQ(4:7) | K0 | 1,5,10,| I | DMA Channel Request: an active-low signal that |
| | | 14 | | is used to request service from one of four |
| | | | | user-definable DMA channels. |
| | | | | |
| -WR | K0 | 20 | O | Write: is the 80C186 write data strobe. This |
| | | | | signal is also driven during DMAPIC DMA cycles. |
| | | | | |
| -ZILOG DS | K2 | 43 | O | Data Strobe: a signal that is used to strobe |
| | | | | data into or out of the CIO. |
| | | | | |
| ZILOG R/-W | K2 | 37 | O | This signal indicates a read from, or a write |
| | | | | to, the CIO, respectively. |
| | | | | |
| 14.7 MHZ | K2 | 39 | O | 14.7456 MHz Clock: a signal that is used to |
| | | | | clock the DUSCC chips on the co-processor |
| | | | | adapter card. |
| | | | | |
| 7.3 MHZ | K2 | 32 | O | 7.3728 MHz Clock: a signal that is used to |
| | | | | clock the CIO chips on the co-processor |
| | | | | adapter card. |
| | | | | |
| +5V | K2 | 6,12,18| O | +5 Vdc Power |
| | | 24,30 | | |
| | | | | |
| GND | K2 | 3,9,15,| O | Signal and Power Ground |
| | | 21,27, | | |
| | | 36,42, | | |
| | | 48,54, | | |
| | | 60 | | |
| | | | | |
| +12V | K1 | 9,23 | O | +12 Vdc Power |
| | | | | |
| -12V | K1 | 2,16 | O | -12 Vdc Power |
+----------------+-----------+--------+-----+-------------------------------------------------+
The co-processor adapter card presents a partial 80C186 signal set at the IB interface. This partial signal set consists of the following signals:
AD(8:15)
** BAD(0:7)
CLKO
SRDY
ALE
RD
WR
BHE
** This is the low-order byte of the 80C186
multiplexed address data bus.
A 74F245 transceiver is used to buffer the signals of the bus.
The direction of this transceiver is controlled by the DMAPIC gate array.
The direction of the transceiver is reversed for a read operation
for specific I/O address decodes only.
The following is a list of the IB chip selects and address ranges
that the DMAPIC issues to reverse the transceiver
direction for a read operation:
Timing
Signal Address Diagram
-SCC2 CS [1A00h-1AFFh] Figure 21
-SCC3 CS [1B00h-1BFFh] Figure 21
-IO CS [F000h-FFFFh] Figure 22
-RDID86 [86h] Figure 23
-ROS CS [E000h-EFFFh] Figure 24
The transceiver is also turned around during the SCC2 and SCC3 interrupt
acknowledge cycles to allow the vector to pass to the 80C186.
The I/O space provided for use by the Interface Board is indicated in the Interface Board I/O Address Map in Figure 5. Chip selects to the IB interface decode various I/O address ranges.
An 8-bit output port at I/O address 800h provides general-purpose control lines to the IB interface. This register is read and writable from the 80C186.
The co-processor adapter supports DMA cycles to the Interface Board. A DMA cycle consists of two independent bus cycles run contiguously. A DMA write operation consists of an I/O read bus cycle followed by a memory write bus cycle. (See Figure 18.) A DMA read operation consists of a memory read bus cycle followed by an I/O write bus cycle. (See Figure 19.) Each individual bus cycle follows the timing of an 80C186 bus cycle. The I/O portion of the DMA cycle should be to an address range defined by the I/O CS signal. The I/O CS signal will be driven active with the timings provided. Alternately, the regions of the Interface Board's I/O space allotted for DUSCC2 and DUSCC3 can be used for DMA. The I/O chip select is not active in this region, and the I/O portion of the DMA cycle is a fixed 3-wait-state cycle (Ready is not sampled).
Eight DMA request signals are provided at the IB interface for use by devices on the IB that require DMA. Each DMA request can be programmed to support DMA read or DMA write operations. No explicit DMA acknowledge signals are supported. Logic must exist on the IB to create the DMA acknowledge signal in response to the I/O half of the DMA cycle.
The -EOP signal is supported for both DMA write and DMA read operations. For DMA write operations, the -EOP signal is driven active by the DMA device synchronous with the last transfer of a DMA block transfer. The DMA controller can be programmed to chain to a new data buffer and continue servicing DMA requests, or it can be programmed to stop DMA transfers in response to this signal. For DMA read operations, -EOP is driven active by the DMA controller upon reaching the terminal count (transfer count = 0) condition. The DMA controller can be programmed to chain to a new data buffer and continue servicing DMA requests, or it can be programmed to stop DMA transfers upon reaching terminal count. The -EOP signal must driven by an open-drain/open-collector driver if it is used. A pull-up resistor is provided on the co-processor adapter card.
Data is driven active by the DMA controller for a DMA read operation with the same timings as the 80C186, relative to CLKOUT and -WR. Data must be valid on the buffered low-order byte of the 80C186 address and data (BAD) bus for a DMA write operation with the same timings as the 80C186, relative to CLKOUT and -RD. Cycles can be extended using DBSRDY, with the timings provided.
Figure 18. DMA Write Operation
+-+ +-+
ALE -----------+ +------------+ +---------------
---------------+ +-------------------
-RD +--------+ (I/O Read)
--------------+ +------------------
-IO CS +----------+
------------------------------+ +----
-WR +--------+ (Memory Write)
-->|t1|<--
|<--- t2 -->|
------+ +----
-DMAREQx +--//----------------+
-->| t3 |<--
-->| t4 |<--
-------------------+ +---------------
-EOP +---------+
-->|t5 |<--
Min / Max
-----------
t1 - / 0 ns -RD inactive to -DMAREQx inactive
t2 0 / - ns -DMAREQ inactive from -RD active
t3 80 / - ns -EOP active setup to -RD inactive
t4 0 / 100 ns -RD inactive to -EOP released (ignore RC restore)
t5 0 / - ns -RD active to -EOP active
Note: -DMAREQx is driven active asynchronously. It need not be driven
inactive in between DMA cycles if more requests are pending. A chip
select qualified by -RD should be used to create a DMA acknowledge
if necessary.
Timings t1 and t2 imply that the -DMAREQx signal should be removed
during the period while -RD is active.
+-+ +-+
ALE -----------+ +------------+ +---------------
---------------+ +-------------------
-RD +--------+ (Memory Read)
-----------------------------+ +---
-IO CS +----------+
------------------------------+ +----
-WR +--------+ (I/O Write)
-->|t6|<--
|<--- t7 -->|
------+ +----
-DMAREQx +--//-------------------------------+
-->|t8 |<--
-->| t9 |<--
----------------------------------+ +---------------
-EOP +---------+
Min / Max
-----------
t6 - / 0 ns -WR inactive to -DMAREQx inactive
t7 0 / - ns -DMAREQ inactive from -WR active
t8 70 / 90 ns -WR active to -EOP active
t9 80 / 200 ns -WR inactive to -EOP inactive
Note: -DMAREQx is driven active asynchronously. It need not be driven
inactive in between DMA cycles if more requests are pending. A chip
select qualified by -WR should be used to create a DMA acknowledge
signal if necessary.
Timings t6 and t7 imply that the -DMAREQx signal should be removed
during the period while -WR is active.
Two interrupt lines are provided for IB devices to interrupt the 80C186. Each interrupt line is coupled with an interrupt acknowledge signal that is used by the interrupting device to provide an interrupt vector back to the 80C186 processor. All devices using the interrupt signals must be capable of providing an interrupt vector back to the 80C186 when the interrupt acknowledge cycle occurs.
The interrupt signal is level sensitive. The device must activate (active low) the interrupt signal and hold it active until reset by software writing to a "clear interrupt" port. A clear interrupt port is a requirement of a device using an interrupt signal. A write to the clear interrupt port should deactivate the interrupt signal. The software then issues the appropriate DMA_EOI command (an I/O write to address 322Xh). The issuance of the DMA_EOI should not occur until the hardware guarantees that the interrupt signal is inactive. Issuance of the DMA_EOI re-enables interrupts on that interrupt level. See Figure 20.
For more information on the clearing of interrupts, refer to the appropriate Hardware Technical Reference manual, either the IBM Realtime Interface Co-Processor Portmaster Adapter/A Hardware Technical Reference or the IBM Realtime Interface Co-Processor Multiport Adapter, Model II Hardware Technical Reference.
Figure 20. Interrupt Request and Acknowledge Timing
The following hardware and software mechanisms are coupled together.
CON2-PIN 34: -SCC2 INT REQ --+
CON2-PIN 35: -SCC2 INTACK +-- Level 2 interrupt
DMA_EOI2: Address 3222h -+
CON2-PIN 02: -SCC3 INT REQ --+
CON2-PIN 08: -SCC3 INTACK +-- Level 3 interrupt
DMA_EOI3: Address 3223h -+
1 4 5 6
-SCC INT REQ -----+ +--------------
+-----------------------------------//--+
2 3
-SCC INTACK ---------//------+ +-+ +--------------------------
+---+ +---------+
/--------\
BAD0-7 -------------------------| VECTOR |------
\--------/
1. Device asserts interrupt signal (asynchronously).
2. 80c186 responds with interrupt acknowledge cycle (two pulses of -SCC INTACK
signal)
3. Device places its 8-bit interrupt vector on BAD bus. Device can place
vector on bus during both cycles, but the bus is only read by the 80C186
during the second cycle.
4. Interrupt handling routine resets interrupt signal by accessing device-
specific clear interrupt port.
5. Interrupt handling routine issues appropriate DMA_EOI command to re-enable
interrupt on this level. Only issue this when -SCC INT REQ is guaranteed
inactive by the device-specific hardware.
6. Interrupt handling routine issues 80C186 processor EOI, then exits from
interrupt subroutine.
+-+ +-+
ALE ----------------+ +------+ +-----------------------------
-SCCx CS (high)---------------------------------------------------------
t6
-->| |<-- t3,t4
-->| |<--
|<-t1->| |<----- t2 ----->|
-SCC INTACK ---------//------+ +-+ +---------------
+------+ +----------------+
/--------\
BAD0-7 -----------------------------------| VECTOR |------
\--------/
|<- t5 ->|
Min / Max
-------------
t1 200 / 280 ns Intack pulse width first cycle
t2 440 / 480 ns Intack pulse width second cycle
t3 0 / - ns Vector hold time from intack inactive
t4 0 / 20 ns BAD bus tristated from intack inactive
t5 0 / 300 ns Vector valid from intack active
t6 200 / 280 ns Intack inactive pulse width
Note: ALE and -SCCx CS shown for reference only.
The Adapter I/O map has two regions defined for use by DUSCCs or DUSCC-like devices. Chip selects and separate read and write signals have been provide specifically for two additional DUSCCs; however, any IB device can take advantage of these signals if the timings are closely adhered to. See Figure 21.
Figure 21. DUSCC Write and Read Signals
DUSCC Write
T4 T1 T2 T3 TW TW TW T4 T1
-+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +
+-----+
ALE --+ +--
|<---------- t1 ------------>|
--+ +--
-SCCx CS +----------------------------+
|<--------- t2 ----------->|
--+ +--
-DUSCC WR +--------------------------+
t3 t4
-->| |<-- -->| |<--
/----------------------------\
BAD0-7 ------| WRITE DATA |----
\----------------------------/
DUSCC Read
T4 T1 T2 T3 TW TW TW T4 T1
-+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +
+-----+
ALE --+ +--
|<---------- t1 ------------>|
--+ +--
-SCCx CS +----------------------------+
|<--------- t2 ----------->|
--+ +--
-DUSCC RD +--------------------------+
t6,t7
|<---- t5 ------>| -->| |<--
/---------\
BAD0-7 -----| READ DATA |----
\---------/
Min / Max
-------------
t1 360 / 400 ns -SCCx CS pulse width for read or write
t2 350 / 390 ns -DUSCC WR or -DUSCC RD pulse width
t3 10 / - ns Write data setup to -DUSCC WR active
t4 10 / - ns Write data hold from -DUSCC WR inactive
t5 0 / 270 ns Read data valid from -DUSCC RD active
t6 0 / - ns Read data hold from -DUSCC RD inactive
t7 0 / 20 ns BAD bus tristated from -DUSCC RD inactive
Note: CLKOUT and ALE are shown for reference only. No relationships to these
signals are guaranteed. Cycles to the -SCCx CS address region default
to 3 wait states. These cycles cannot be extended using DBSRDY.
Chip select signal -IO CS is a raw address decode over the range of from F000h-FFFFh, which is in the Adapter I/O address range. See Figure 22. The address range FF00h to FFFFh is reserved for the 80C186. This reserve range requires the IO CS signal to be further qualified by address bit AD11 so that no IB device is selected when the 80C186 accesses the reserved I/O region.
Figure 22. I/O Chip Select Signals (Write and Read Data)
I/O Chip Select (Write Data)
T4 T1 T2 T3 T4
-+ +--+ +--+ +--+ +--+ +--+ +-
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE --+ +-----------------+ +-
t1 t2
-->| |<-- -->| |<--
--+ +--
-WR +-----------+
t3 t4
-->| |<-- -->| |<--
--+ +--
-IO CS (See Note) +-----------------+
t5 t6
-->| |<-- -->| |<--
/----------\
BAD0-7 -----| WRITE DATA |----
\----------/
I/O Chip Select (Read Data)
T4 T1 T2 T3 T4
-+ +--+ +--+ +--+ +--+ +--+ +-
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE --+ +-----------------+ +-
t1 t2
-->| |<-- -->| |<--
--+ +--
-RD +-----------+
t3 t4
-->| |<-- -->| |<--
--+ +--
-IO CS (See Note) +-----------------+
t8,t9
-->| |<--
/-------\
BAD0-7 ------|READ DATA|----
t7 \-------/
-->| |<--
Min / Max
-------------
t1 5 / 37 ns T2 fall to -RD or -WR active
t2 5 / 37 ns T4 fall to -RD or -WR inactive
t3 0 / 35 ns T1 rise to -IO CS active
t4 0 / 110 ns T4 rise to -IO CS inactive
t5 7 / 46 ns T2 fall to write data valid
t6 30 / - ns Write data hold from T4 rise
t7 0 / 95 ns -RD active to read data valid
t8 0 / - ns Read data hold from -RD inactive
t9 0 / 20 ns BAD bus tristated from -RD inactive
Note: CLKOUT and ALE are shown for reference only. No relationships to these
signals are guaranteed. I/O CS is not defined when ALE is active-high.
Cycles to -IO CS address range default to 0 wait states. These cycles
can be extended using DBSRDY.
The -ROS CS signal is an active-low chip select over the I/O address range of from E000h-EFFFh. This chip select has been provided to eliminate the need for an Interface Board to decode the IB ROS area. The -ROS CS signal is active during 80C186 read and write operations; this facilitates the use of devices other than a PROM in this I/O region.
It should be noted that if the IB PROM is not implemented, the following two I/O read conditions must be satisfied as stated below. (For additional information, see "PROM ID".)
The -RDID86 chip select signal provides an active-low decode for a read of I/O address 86h. This signal can be used to directly gate the Interface Board ID onto the address/data bus. The timing diagram for the RDID86 chip select signal is shown in Figure 23.
Figure 23. RDID86 Chip Select Signals
RDID86 Chip Select
T4 T1 T2 T3 T4
-+ +--+ +--+ +--+ +--+ +--+ +--
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE ----+ +-----------------+ +-
/------\
AD8-15 -----| ADDR |------
BAD0-7 \------/
t1 t2
-->| |<-- -->| |<--
--------+ +------
-RDID86 +---------------------+
-------+ +------
-RD +-------------------+
-->| t3 |<--
/---------\
BAD0-7 -------| DATA |--------
\---------/
Min / Max
---------
t1 5 / 15 -RDID86 active low from address valid
t2 5 / 15 -RDID86 inactive delay from -RD inactive
t3 22 / - Data setup to falling edge of T3
The timing diagram for the ROS chip select signal is
shown in
Figure 24.
Figure 24. ROS Chip Select Signals
ROS Chip Select
T4 T1 T2 T3 TW TW T4 T1
-+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +-
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE --+ +-----------------------------+ +-
t1 t2
-->| |<-- -->| |<--
--+ +--
-WR +-----------------------+
t3 t4
-->| |<-- -->| |<--
--+ +--
-ROS CS +-----------------------------+
t5 t6
-->| |<-- -->| |<--
/----------------------\
BAD0-7 -----| WRITE DATA |----
\----------------------/
T4 T1 T2 T3 TW TW T4 T1
-+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +-
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE --+ +-----------------------------+ +-
t1 t2
-->| |<-- -->| |<--
--+ +--
-RD +-----------------------+
t3 t4
-->| |<-- -->| |<--
--+ +--
-ROS CS +-----------------------------+
t8,t9
|<---- t7 ----->| -->| |<--
/-------\
BAD0-7 ---------------|READ DATA|----
\-------/
Min / Max
-------------
t1 5 / 37 ns T2 fall to -RD or -WR active
t2 5 / 37 ns T4 fall to -RD or -WR inactive
t3 0 / 35 ns T1 rise to -ROS CS active
t4 0 / 110 ns T4 rise to -ROS CS inactive
t5 7 / 46 ns T2 fall to write data valid
t6 30 / - ns Write data hold from T4 rise
t7 0 / 240 ns -RD active to read data valid
t8 0 / - ns Read data hold from -RD inactive
t9 0 / 20 ns BAD bus tristated from -RD inactive
Note - CLKOUT and ALE are shown for reference only. No relationships to these
signals are guaranteed. Cycles to -ROS CS address range default to
2 wait states. These cycles can be extended using DBSRDY.
Figure 25 shows the timing diagram for Interface Board Sync Ready (DBSRDY).
Figure 25. Interface Board Sync Ready (DBSRDY)
T4 T1 T2 TW TW T3 T4
-+ +--+ +--+ +--+ +--+ +--+ +--+ +-
CLKOUT +--+ +--+ +--+ +--+ +--+ +--+ +--+
+-----+ +-----+
ALE --+ +-----------------------+ +-
t1 t2
-->| |<-- -->| |<--
---+ +-----
DBSRDY +---------+
Min / Max
---------
t1 - / 20 T2 rise to DBSRDY inactive
t2 -5 / 20 T state rise to DBSRDY active
Note: Cycles to the -IO CS or -ROS CS region can be extended to longer
than its default cycle time through the use of DBSRDY. Logic should
drive DBSRDY inactive with the first rising edge after a valid chip
select, and hold it inactive for an integral number of clocks until
data is valid (read) or data is latched (write).
Cycles to the region defined by -SCCx CS should not be extended
beyond the default 3 wait states.
The IB ROS provides 4KB of address space, which is accessible in I/O space from E000h to EFFFh. Structures, which are used to provide information about the communication ports, have been architected in the IB ROS. There are eight IB ROS structures:
The structure, Interface Board Header, shown in Figure 27 contains fields which describe the contents of the IB ROS. This section must be implemented if an IB ROS is installed. The use of the IB ROS is indicated by the setting of the IB ROS Presence bit. If this bit indicates that the ROS conforms to Realtime Control Microcode Logical Control Line Services (LCLS), then the co-processor adapter card ROS will use the data provided in the IB ROS to supply the Port Configuration Descriptor (PCD) with information about the IB. If this bit indicates that the ROS does not conform, then the co-processor adapter card ROS will ignore all information stored in the IB ROS, when building the PCD.
The structure, Hardware Information for Ports Residing on the Interface Board, shown in Figure 28 is used to indicate the number, type, and sync capabilities of the communications controllers installed on the IB. It also indicates the presence of CIOs installed on the IB. Currently, only Signetics DUSCCs may be described.
The structure, Tx and Rx DMA Channel Numbers, shown in Figure 29 is used to indicate which DMA channels are transmit, receive, or configurable. The transmit channel numbers are listed first; these are followed by the receive channel numbers. Then, 0's will be used as filler for the remainder of this field when there are fewer than 32 DUSCC ports installed on the co-processor adapter card and the IB combined. For example, the Eight-Port RS-232 Interface Board/A has the following data: 09 0B 0D 0F for the transmit channel numbers; 08 0A 0C 0E for the receive channel numbers; and 00...00 to fill out the remaining bytes.
The structure, CIO Data Direction Register Information, shown in Figure 30 is used by the co-processor adapter card ROS when configuring the CIOs following the CIO POST tests. It also is used by calls to the PROM Services and Diagnostic Test CIO reset routines. This data is not incorporated into the PCD.
The structure, Pointers to Port Information, shown in Figure 31 provides a list of co-processor adapter I/O addresses, from which the port-specific data can be read.
The structure, Port Information, contains data describing six output signals and six input signals for each port installed on the IB. Figure 35, in six parts, illustrates the data fields required to describe each port. The output signals are HRS(OUT), TXBLK, CLOCK, RTS, DTR, and CONTROL. For each output signal, the following information is required:
Note: Careful attention must be paid to the values used for activation logic. This is true especially when the CIO is programmed for all-inverting mode.
The six input signals are RI, HRS(IN), CTS, DCD, DSR, and INDICATE. For each input signal, the following information is required:
The final field for each port describes how the signals on the port are wrapped.
The structure, Read Cable ID Routine, shown in Figure 33 is architected to allow the IB ROS to supply a routine which, when called, returns the cable ID of a particular port. The co-processor adapter card ROS will call this routine if the following conditions are met:
The above conditions are checked by the co-processor adapter card ROS in two instances. They are checked just before ROS enters the idle loop, following POST, and they are checked each time the Diagnostic routine, CREATE PCDHCD, INT FEh, AH=13h is called. For each port which satisfies the above conditions, the co-processor adapter card ROS will call the routine, which it has downloaded into a scratch area, and update the PCD, port-type field, for that port. The Read Cable ID Routine must pass back a port-type value in register AL for this purpose.
Use of the Read Cable ID Routine is described in section Read Cable_ID Executable Routine.
The structure, Interface Board ROS Checksum, shown in Figure 34 contains the checksum of the IB ROS. It is used by the co-processor adapter card ROS to verify the data integrity of the IB ROS. If a checksum error is detected:
Figure 26 shows the I/O address map of the Interface Board ROS.
+--------+--------+------------------------+------------------------+ | I/O | Length | | | | Address| Bytes | Field | Comments | | (hex) | (hex) | | | +--------+--------+------------------------+------------------------+ | E000h | 1F | Interface Board header | | +--------+--------+------------------------+------------------------+ | E01Fh | 10 | Hardware information | | | | | for ports residing on | | | | | Interface Board | | +--------+--------+------------------------+------------------------+ | E02Fh | 2n | Tx and Rx DMA channel | n = Maximum number of | | | | numbers | DUSCC ports | | | | | possible (20h) | +--------+--------+------------------------+------------------------+ | E06Fh | 18 | CIO data direction | | | | | register information | | +--------+--------+------------------------+------------------------+ | E087h | 2n | Pointers to port | n = Number of DUSCC | | | | information | ports installed on | | | | | base card and on | | | | | Interface Board | +--------+--------+------------------------+------------------------+ | | 3Dn | Port information | n = Number of DUSCC | | | | | ports installed on | | | | | base card and on | | | | | Interface Board | +--------+--------+------------------------+------------------------+ | E867h |Variable| Read cable ID routine | See Read Cable ID | | | | | Routine Description | | | | | for length. | +--------+--------+------------------------+------------------------+ | EFFEh | 2 | Interface Board ROS | | | | | checksum | | +--------+--------+------------------------+------------------------+
Figure 27 through Figure 35 show the format of the Interface Board ROS.
Figure 27. Interface Board Header
+-------+-----------------+----------------------------------------+ | Offset| Description | Comments | | (hex) | | | +-------+-----------------+----------------------------------------+ | 00h | Interface Board | A PROM ID must be assigned to the | | | ROS ID | Interface Board ROS. | +-------+-----------------+----------------------------------------+ | 01h | Interface Board | 00h = ROS conforms to RCM LCLS.* | | | ROS presence | 01h = ROS does not conform to RCM LCLS.| +-------+-----------------+----------------------------------------+ | 02h | Interface Board | | | | ROS level | | +-------+-----------------+----------------------------------------+ | 03h | Port count | Total number of ports | | | | (base card and Interface Board). | +-------+-----------------+----------------------------------------+ | 04h -| Copyright notice| '(C) COPYRIGHT XYZ CORP 1989'** | | 1Eh | | | +-------+-----------------+----------------------------------------+ | * RCM LCLS is an abbreviation for Realtime Control Microcode | | Logical Control Line Services. | | ** The year should be updated as necessary. | +------------------------------------------------------------------+Figure 28. Hardware Information for Ports Residing on Interface Board
+-------+-----------------+----------------------------------------+ | Offset| Description | Comments | | (hex) | | | +-------+-----------------+----------------------------------------+ | 00h | Interface Board | Number of ports on Interface Board. | | | port count | | +-------+-----------------+----------------------------------------+ | 01h -| Communications | CC15 . . . . . . . . . . . . CC1 CC0 | | 02h | controller (CC) | One bit per CC: | | | presence on | 0h = CC not present | | | Interface Board | 1h = CC present. | +-------+-----------------+----------------------------------------+ | 03h | CIO presence on | C7 C6 C5 C4 C3 C2 C1 C0 | | | Interface Board | One bit per CIO: | | | | 0h = CIO not present | | | | 1h = CIO present. | +-------+-----------------+----------------------------------------+ | 04h -| Sync capability | One bit per port: | | 07h | | 0h = Sync not present | | | | 1h = Sync present. | +-------+-----------------+----------------------------------------+ | 08h -| Type of | Two bits per port: | | 0Fh | communications | 00h = Reserved | | | controller | 01h = DUSCC | | | | 10h = Reserved | | | | 11h = Extended Type | | | | (see next eight bytes | | | | for CC Type). | +-------+-----------------+----------------------------------------+Figure 29. Tx and Rx DMA Channel Numbers
+-------+-----------------+-----------------------------------------+ | Offset| Description | Comments | | (hex) | | | +-------+-----------------+-----------------------------------------+ | 00h -| DMA channel no. | One byte per port: | | (n-1)h| for Tx | n = No. of ports on Interface | | | | Board. | | | | 00h-FDh = Channel number for Tx. | | | | FEh = Only one DMA channel per port | | | | (configurable). | | | | FFh = No DMA for Tx. | +-------+-----------------+-----------------------------------------+ | nh -| DMA channel no. | One byte per port: | |(2n-1)h| for Rx | n = No. of ports on Interface | | | | Board. | | | | 00h-FDh = Channel number for Rx. | | | | FFh = No DMA for Rx. | | | | = If Tx DMA = FEh, then Rx DMA | | | | is the channel number of the | | | | configurable channel. | +-------+-----------------+-----------------------------------------+ | 2nh -| Filler | This field should be filled with 0s; | | 3Fh | | it will be present only when the number | | | | of ports on the Interface Board is less | | | | than the maximum number of DUSCC ports | | | | possible (20h). | +-------+-----------------+-----------------------------------------+Figure 30. CIO Data Direction Register Information
+--------+------------------+-----------------------------+ | Offset | Description | Comments | | (hex) | | | +--------+------------------+-----------------------------+ | 00h | CIO 0 port A | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+ | 01h | CIO 0 port B | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+ | 02h | CIO 0 port C | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+ | 03h | CIO 1 port A | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+ | 04h | CIO 1 port B | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+ | 05h | CIO 1 port C | One bit per control signal: | | | data direction | 0 = Output | | . | . . | 1 = Input. | | . | . . | . | | . | . . | . | | . | . . | . | | | | | | 17h | CIO 7 port C | One bit per control signal: | | | data direction | 0 = Output | | | | 1 = Input. | +--------+------------------+-----------------------------+Figure 31. Pointers to Port Information
+--------+---------------------+--------------------------+ | Offset | Description | Comments | | (hex) | | | +--------+---------------------+--------------------------+ | 00h | Pointer to 1st port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 02h | Pointer to 2nd port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 04h | Pointer to 3rd port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 06h | Pointer to 4th port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 08h | Pointer to 5th port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 0Ah | Pointer to 6th port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 0Ch | Pointer to 7th port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+ | 0Eh | Pointer to 8th port | See Port X Information | | | information | Table (Figure 35) | | . | . | . | | . | . | . | | . | . | . | | | | | | (2x-1)h| Pointer to xth port | See Port X Information | | | information | Table (Figure 35) | +--------+---------------------+--------------------------+Figure 32. Port Information
+--------+----------------------------+---------------------------+ | Offset | Description | Comments | | (hex) | | | +--------+----------------------------+---------------------------+ | | For each port on the | | | | Interface Board, the | | | | "Port X Information" | | | | Table (Figure 35) | | | | is repeated. | | +--------+----------------------------+---------------------------+Figure 33. Read Cable ID Routine
+--------+----------------------------+---------------------------+ | Offset | Description | Comments | | (hex) | | | +--------+----------------------------+---------------------------+ | 00h - | Length of routine | Length is in bytes | | 01h | | | +--------+----------------------------+---------------------------+ | 02h | Routine to read cable ID | | | | and convert it into | | | | interface type identifier | | | | for each port | | +--------+----------------------------+---------------------------+ | Note: This field is optional. | +-----------------------------------------------------------------+Figure 34. Interface Board ROS Checksum
+--------+---------------------------+---------------------------+ | Offset | Description | Comments | | (hex) | | | +--------+---------------------------+---------------------------+ | 00h | Two-byte checksum, with | | | | the most-significant bits | | | | at offset 0FFFh and the | | | | least-significant bits at | | | | offset 0FFEh. | | +--------+---------------------------+---------------------------+Figure 35. Port X Information
+--------+--------------+-------------------------+--------------------------+ | Offset | Field Name | Description | Comments | | (hex) | | | | +--------+--------------+-------------------------+--------------------------+ | 00h | PORT_NUMBER | CC port number | CC is an abbreviation | | | | | for serial communications| | | | | controller | +--------+--------------+-------------------------+--------------------------+ | 01h | INT_TYPE | Interface Type | 00h = RS-232-D | | | | | 01h = RS-422-A | | | | | 02h = V.35 | | | | | 03h = X.21 | | | | | 04h-FDH = Reserved | | | | | FEh = Interface | | | | | unknown | | | | | FFh = Configurable | | | | | by cable. | +--------+--------------+-------------------------+--------------------------+ | 02h - | LCLS_SUPPORT | Indicates which LCLS | Not currently supported. | | 03h | | services are supported | | +--------+--------------+-------------------------+--------------------------+ | 04h - | HRS(OUT) | Port address or CIO port| For all entries below, | | 05h | PORT_ADDR | number if port type = | the CIO port numbering | | | | 00h or 01h | scheme is as follows: | | | | | 0h = CIO0, port A | | | | | 1h = CIO0, port B | | | | | 2h = CIO1, port A | | | | | 3h = CIO1, port B | | | | | 4h = CIO1, port C | | | | | 5h = CIO2, port A | | | | | 6h = CIO2, port B | | | | | 7h = CIO2, port C | | | | | . | | | | | . | | | | | . | | | | | 16h = CIO7, port C | +--------+--------------+-------------------------+--------------------------+ | 06h | HRS(OUT) | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 07h | HRS(OUT) | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | FFh = HRS(OUT) not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 08h | HRS(OUT) | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate HRS(OUT); | | | | signal | output logic 1 to | | | | | deactivate. | | | | | 01h = Output logic 1 to | | | | | activate HRS(OUT); | | | | | output logic 0 to | | | | | deactivate. | +--------+--------------+-------------------------+--------------------------+ | 09h - | TXBLK | Port address or CIO port| | | 0Ah | PORT_ADDR | number if port type = | | | | | 00h or 01h | | +--------+--------------+-------------------------+--------------------------+ | 0Bh | TXBLK | Register bit position | | | | BIT_ NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 0Ch | TXBLK | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | FEh = RTS is required to | | | | | enable transmit | | | | | FFh = TXBLK not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 0Dh | TXBLK | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate TXBLK; | | | | signal | output logic 1 to | | | | | deactivate. | | | | | 01h = Output logic 1 to | | | | | activate TXBLK; | | | | | output logic 0 to | | | | | deactivate. | +--------+--------------+-------------------------+--------------------------+ | 0Eh - | CLOCK | Port address or CIO port| | | 0Fh | PORT_ADDR | number if port type = | | | | | 00h or 01h | | +--------+--------------+-------------------------+--------------------------+ | 10h | CLOCK | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 11h | CLOCK | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | FFh = CLOCK not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 12h | CLOCK | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate DTE CLK; | | | | signal | output logic 1 to | | | | | activate DCE CLK. | | | | | 01h = Output logic 1 to | | | | | activate DTE CLK; | | | | | output logic 0 to | | | | | activate DCE CLK. | +--------+--------------+-------------------------+--------------------------+ | 13h - | RTS | Port address or CIO port| This field is not used | | 14h | PORT_ADDR | number if port type = | if the signal is from | | | | 00h or 01h | the CC. | +--------+--------------+-------------------------+--------------------------+ | 15h | RTS | Register bit position | This field is not used | | | BIT_NO | for this signal | if the signal is from | | | | | the CC. | +--------+--------------+-------------------------+--------------------------+ | 16h | RTS | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | 03h = DUSCC | | | | | FFh = RTS not supported. | +--------+--------------+-------------------------+--------------------------+ | 17h | RTS | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate RTS; | | | | signal | output logic 1 to | | | | | deactivate RTS. | | | | | 01h = Output logic 1 to | | | | | activate RTS; | | | | | output logic 0 to | | | | | deactivate RTS. | +--------+--------------+-------------------------+--------------------------+ | 18h - | DTR | Port address or CIO port| This field is not used | | 19h | PORT_ADDR | number if port type = | if the signal is from | | | | 00h or 01h | the CC. | +--------+--------------+-------------------------+--------------------------+ | 1Ah | DTR | Register bit position | This field is not used | | | BIT_NO | for this signal | if the signal is from | | | | | the CC. | +--------+--------------+-------------------------+--------------------------+ | 1Bh | DTR | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | 03h = DUSCC | | | | | FFh = DTR not supported. | +--------+--------------+-------------------------+--------------------------+ | 1Ch | DTR | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate DTR; | | | | signal | output logic 1 to | | | | | deactivate DTR. | | | | | 01h = Output logic 1 to | | | | | activate DTR; | | | | | output logic 0 to | | | | | deactivate DTR. | +--------+--------------+-------------------------+--------------------------+ | 1Dh - | CONTROL | Port address or CIO port| | | 1Eh | PORT_ADDR | number if port type = | | | | | 00h or 01h | | +--------+--------------+-------------------------+--------------------------+ | 1Fh | CONTROL | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 20h | CONTROL | Describes device which | 00h = Port A or Port B | | | PORT_TYPE | controls this signal | of CIO | | | | | 01h = Port C of CIO | | | | | 02h = Any 8-bit | | | | | read/write register| | | | | FFh = CONTROL not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 21h | CONTROL | Describes logical level | 00h = Output logic 0 to | | | ACTIVATION | used to control this | activate CONTROL; | | | | signal | output logic 1 to | | | | | deactivate. | | | | | 01h = Output logic 1 to | | | | | activate CONTROL; | | | | | output logic 0 to | | | | | deactivate. | +--------+--------------+-------------------------+--------------------------+ | 22h | RI | CIO port number | 00h-16h = CIO port | | | PORT_NO | | number | | | | | FFh = RI not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 23h | RI | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 24h | RI | Describes logical level | 00h = RI is active when | | | ACTIVATION | used to control this | read logic 0; | | | | signal | RI is not active | | | | | when read logic 1. | | | | | 01h = RI is active when | | | | | read logic 1; | | | | | RI is not active | | | | | when read logic 0. | +--------+--------------+-------------------------+--------------------------+ | 25h | HRS(IN) | CIO port number | 00h-16h = CIO port number| | | PORT_NO | | FFh = HRS(IN) not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 26h | HRS(IN) | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 27h | HRS(IN) | Describes logical level | 00h = HRS(IN) is active | | | ACTIVATION | used to control this | when read logic 0; | | | | signal | HRS(IN) is not | | | | | active when read | | | | | read logic 1. | | | | | 01h = HRS(IN) is active | | | | | when read logic 1; | | | | | HRS(IN) is not | | | | | active when read | | | | | read logic 0. | +--------+--------------+-------------------------+--------------------------+ | 28h | CTS | Port Number for CTS | 00h-16h = CIO port number| | | PORT_NO | | FEh = From CC | | | | | FFh = CTS not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 29h | CTS | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 2Ah | CTS | Describes logical level | 00h = CTS is active when | | | ACTIVATION | used to control this | read logic 0; | | | | signal | CTS is not active | | | | | when read logic 1. | | | | | 01h = CTS is active when | | | | | read logic 1; | | | | | CTS is not active | | | | | when read logic 0. | +--------+--------------+-------------------------+--------------------------+ | 2Bh | DCD | CIO port number | 00h-16h = CIO port number| | | PORT_NO | | FEh = From CC | | | | | FFh = DCD not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 2Ch | DCD | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 2Dh | DCD | Describes logical level | 00h = DCD is active when | | | ACTIVATION | used to control this | read logic 0; | | | | signal | DCD is not active | | | | | when read logic 1. | | | | | 01h = DCD is active when | | | | | read logic 1; | | | | | DCD is not active | | | | | when read logic 0. | +--------+--------------+-------------------------+--------------------------+ | 2Eh | DSR | CIO port number | 00h-16h = CIO port number| | | PORT_NO | | FEh = From CC | | | | | FFh = DSR not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 2Fh | DSR | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 30h | DSR | Describes logical level | 00h = DSR is active when | | | ACTIVATION | used to control this | read logic 0; | | | | signal | DSR is not active | | | | | when read logic 1. | | | | | 01h = DSR is active when | | | | | read logic 1; | | | | | DSR is not active | | | | | when read logic 0. | +--------+--------------+-------------------------+--------------------------+ | 31h | INDICATE | CIO port number | 00h-16h = CIO port no. | | | PORT_NO | | for ROS and | | | | | diagnostics. | | | | | FFh = DSR not | | | | | supported. | +--------+--------------+-------------------------+--------------------------+ | 32h | INDICATE | Register bit position | | | | BIT_NO | for this signal | | +--------+--------------+-------------------------+--------------------------+ | 33h | INDICATE | Describes logical level | 00h = INDICATE is active | | | ACTIVATION | used to control this | when read logic 0; | | | | signal | INDICATE is not | | | | | active when read | | | | | logic 1. | | | | | 01h = INDICATE is active | | | | | when read logic 1; | | | | | INDICATE is not | | | | | active when read | | | | | logic 0. | +--------+--------------+-------------------------+--------------------------+ | 34h - | WRAP PLUG | This nine-byte field | | 3Ch |N INFORMATION| describes how the | | | | control signals are | | | | wrapped. | | | | -+ | +--------+--------------+----------------------- | | | | | Wrap for RxD | | +--------+--------------+----------------------- | | | | | Wrap for CTS | 00h = Signal not wrapped | +--------+--------------+----------------------- | 01h = Signal wrapped to | | | | Wrap for DSR | TxD | +--------+--------------+----------------------- | 02h = Signal wrapped to | | | | Wrap for DCD | RTS | +--------+--------------+----------------------- > 03h = Signal wrapped to | | | | Wrap for HRS(IN) | DTR | +--------+--------------+----------------------- | 04h = Signal wrapped to | | | | Wrap for TXCIN | HRS(OUT) | +--------+--------------+----------------------- | 05h = Signal wrapped to | | | | Wrap for RXCIN | TXCOUT | +--------+--------------+----------------------- | 06h = Signal wrapped to | | | | Wrap for RI | CONTROL. | +--------+--------------+----------------------- | | | | | Wrap for INDICATE -+ | +--------+--------------+----------------------------------------------------+
A program, CRROS.EXE, is available from the Boca Raton MSP Co-Processor Hardware Development Group. Contact should be made through an IBM Marketing Representative. This interactive module prompts the user to answer questions describing each of the fields contained in the IB ROS. The output of the module is a .ASM file, which can then be assembled, linked, and converted to a HEX file. At this point, the checksum for the IB ROS can be calculated, then added to the Checksum field. Finally, the HEX file can then be used by a PROM burning tool to create the IB ROS. It is not necessary to use CRROS.EXE, nor follow the steps outlined; however, it is a tool available to an IB developer.
Figure 36, in three parts, shows the output of the CRROS.EXE program for an EIA-232 Interface Board. Note, this figure does not show information for ports 1 through 7 as they would be similar to port 0.
Figure 36. .ASM file for EIA-232 IB ROS
CSEG segment byte public
db 10h ;IB PROM ID
db 0 ;IB PROM conformance
db 10h ;IB PROM level
db 8 ;Total number of ports
DB '(C) COPYRIGHT IBM CORP 1989'
db 4 ;Number of ports on IB
dw 3 ;SCCs present on IB
db 0 ;CIOs present on IB
dd 15 ;Sync capability on IB
dd 85 ;Type of SCCs on IB
dd 0 ;Type of SCCs on IB
db 9 ;TX DMA channel number for IB Port 0
db 11 ;TX DMA channel number for IB Port 1
db 13 ;TX DMA channel number for IB Port 2
db 15 ;TX DMA channel number for IB Port 3
db 8 ;RX DMA channel number for IB Port 0
db 10 ;RX DMA channel number for IB Port 1
db 12 ;RX DMA channel number for IB Port 2
db 14 ;RX DMA channel number for IB Port 3
db 56 dup (00) ;Extra bytes
db 0 ;Data direction for CIO 0 Port A
db 255 ;Data direction for CIO 0 Port B
db 0 ;Data direction for CIO 0 Port C
db 255 ;Data direction for CIO 1 Port A
db 255 ;Data direction for CIO 1 Port B
db 254 ;Data direction for CIO 1 Port C
db 0 ;Data direction for CIO 2 Port A
db 0 ;Data direction for CIO 2 Port B
db 0 ;Data direction for CIO 2 Port C
db 0 ;Data direction for CIO 3 Port A
db 0 ;Data direction for CIO 3 Port B
db 0 ;Data direction for CIO 3 Port C
db 0 ;Data direction for CIO 4 Port A
db 0 ;Data direction for CIO 4 Port B
db 0 ;Data direction for CIO 4 Port C
db 0 ;Data direction for CIO 5 Port A
db 0 ;Data direction for CIO 5 Port B
db 0 ;Data direction for CIO 5 Port C
db 0 ;Data direction for CIO 6 Port A
db 0 ;Data direction for CIO 6 Port B
db 0 ;Data direction for CIO 6 Port C
db 0 ;Data direction for CIO 7 Port A
db 0 ;Data direction for CIO 7 Port B
db 0 ;Data direction for CIO 7 Port C
dw -8041 ;Pointer to information of port 0
dw -7980 ;Pointer to information of port 1
dw -7919 ;Pointer to information of port 2
dw -7858 ;Pointer to information of port 3
dw -7797 ;Pointer to information of port 4
dw -7736 ;Pointer to information of port 5
dw -7675 ;Pointer to information of port 6
dw -7614 ;Pointer to information of port 7
db 0 ;CC port number
db 0 ;Type of interface
dw 0 ;Services supported
dw 0 ;Port address for HRS(OUT)
db 0 ;Bit number for HRS(OUT)
db 255 ;Port type for HRS(OUT)
db 0 ;Activation logic HRS(OUT)
dw 0 ;Port address for TXBLK
db 0 ;Bit number for TXBLK
db 254 ;Port type for TXBLK
db 0 ;Activation logic TXBLK
dw 800h ;Port address for CLOCK
db 0 ;Bit number for CLOCK
db 2 ;Port type for CLOCK
db 0 ;Activation logic CLOCK
dw 0 ;Port address for RTS
db 0 ;Bit number for RTS
db 3 ;Port type for RTS
db 0 ;Activation logic RTS
dw 0 ;Port address for DTR
db 0 ;Bit number for DTR
db 0 ;Port type for DTR
db 1 ;Activation logic DTR
dw 0 ;Port address for CONTROL
db 0 ;Bit number for CONTROL
db 255 ;Port type for CONTROL
db 0 ;Activation logic CONTROL
db 2 ;CIO port number for RI
db 0 ;CIO bit number for RI
db 1 ;Activation logic for RI
db 3 ;CIO port number for HRS(IN)
db 0 ;CIO bit number for HRS(IN)
db 1 ;Activation logic for HRS(IN)
db 254 ;CIO port number for CTS
db 0 ;CIO bit number for CTS
db 0 ;Activation logic for CTS
db 254 ;CIO port number for DCD
db 0 ;CIO bit number for DCD
db 0 ;Activation logic for DCD
db 1 ;CIO port number for DSR
db 0 ;CIO bit number for DSR
db 1 ;Activation logic for DSR
db 255 ;CIO port number for INDICATE
db 0 ;CIO bit number for INDICATE
db 0 ;Activation logic for INDICATE
db 1 ;Wrap for RXD
db 2 ;Wrap for CTS
db 3 ;Wrap for DSR
db 2 ;Wrap for DCD
db 3 ;Wrap for HRS(IN)
db 2 ;Wrap for TXCIN
db 5 ;Wrap for RXCIN
db 3 ;Wrap for RI
db 0 ;Wrap for INDICATE
:
:
db 1512 dup (00) ;Extra bytes
dw 0 ;No Cable ID Read Routine
db 1941 dup (00) ;Extra bytes
dw 00000h ;Checksum
CSEG ends
end
The Read Cable_ID Executable Routine resides in the Read Cable ID structure of the IB ROS. This routine, as well as the structure itself, is optional.
While this routine must pass back information to be written to the port type fields in the Port Configuration Descriptor (PCD), it may be used by an IB developer to execute any type of routine. Typical uses may be the reconfiguration of hardware registers or execution of diagnostics. If used for diagnostics, the routine must first check the Secondary Status Byte of the Buffer Control Block, as described in the IBM Realtime Interface Co-Processor Firmware Technical Reference. It is through this field that error information is passed back to the loader. If this field has a non-zero value, then the ROS diagnostics have already detected an error, and any error information passed back to this field by IB diagnostics will overwrite any error data already there. The calling and return sequences for this routine are shown in Figure 37.
Figure 37. Read Cable_ID, Calling and Return Sequence
CABLE_ID PROC
:
:
:
CABLOOP:
MOV AL,BYTE PTR {BX} ;GET PORT TYPE IN AL
CMP AL,0FFH ;IS PORT TYPE configurable ?
JNZ NEXT_ID ; NO...GET NEXT PORT TYPE
CALL CABL_PTR ; YES..EXECUTE ROUTINE
MOV BYTE PTR {BX},AL ; AL = NEW PORT TYPE
NEXT_ID:
INC AH ; INCREMENT PORT NUMBER
INC BX ; INCREMENT PORT TYPE POINTER
LOOP CABLOOP
CABLE_END:
POP DS
POPA
RET
CABLE_ID ENDP
Note: CABL_PTR contains the segment and offset of the Read Cable_ID Routine.
The Read Cable_ID routine must then do an RET to get back to the
calling routine.
As described in the Port Information Structure and shown in Figure 35, the signal set used applies to an EIA-232 interface. It is possible, however, to overlay these fields to describe other control signals. An X.21 interface may be described in the port information fields of an IB ROS by using the following overlays:
TxBLK --> Tx_EN
RTS --> CONTROL
CTS --> INDICATE
CLOCK --> DTE/DCE CLOCK
DSR --> X21S0
DCD --> X21S1
DTR --> X21EN
If Realtime Control Microcode is to be used,
care must be taken when using overlays.
This microcode must recognize the overlays in order to
properly allocate ports.
The co-processor adapter card supplies +5Vdc, +12Vdc, and -12Vdc power to the Interface Board. The co-processor adapter card consumes a maximum current of 2.1 Amperes from the +5Vdc power supply with 2MB of memory and no Interface Board attached. When the 512KB or 1MB versions are used, this number is slightly less. The co-processor adapter card does not consume any power from the +12Vdc or -12Vdc supplies. The target power consumption of an Interface Board should be based on the +5Vdc power used by the co-processor adapter card and the available power on a system-per-slot basis.
Loading of the following signal nets should be minimized. Only one ALS or HCT load is preferred on these signals.
-RD
-WR
BAD(0:7)
AD(0:7)
EALE
CLKO, 14.7456 MHz, 7.3 MHz
Care should be taken to minimize the distance from the Interface Board header pins to the
receiver input of the following signal nets:
-RD
-WR
EALE
CLKO, 14.7456 MHz, 7.3 MHz
To avoid unwanted noise and signal coupling, the EIA communication signals and their respective drivers and receivers should be placed as close to the external connector as possible. Care should also be taken to avoid routing TTL signals between or parallel to the external EIA communication signals.
The co-processor adapter card has a 10-microfarad bulk decoupling capacitor on both the +12Vdc and the -12Vdc lines. The co-processor adapter card has standard per-chip decoupling of 0.1 microfarads, along with some bulk decoupling of 10 microfarads near devices a with large number of simultaneously switching outputs. For EMC considerations on the Portmaster Adapter/A card, ferrite beads have been added to the power and ground pins of the Interface Board header pin housing, as well as the -RD line. These ferrite beads have an approximate impedance of 100 ohms at 75 MHz.
The following IB interface signals are pulled up on the co-processor adapter card. It should be noted that the Interface Board should actively drive high any data or address bits that it requires.
DBSRDY
-SCC(0:3) INT REQ
-CIO(0:1) INT REQ
-BHE
AD(8:15)
BAD(0:7)
-WR
-RD
ZIEOF
-TXREQ(4:7)
-RXREQ(4:7)
An isolated ground plane (frame ground) should be created for the mounting area of the external connector. No digital grounds or signals should tie into this plane. The separated ground should be coupled to the digital ground plane through a 0.01 microfarad capacitor; this is in accordance with the the Card Frame Ground/DC Ground Isolation Section of the IBM Personal System/2 Seminar Proceedings, Volume 5, Number 3, regarding adapter cards.
Since the Interface Board's components face components on the co-processor adapter card, care should be taken regarding the placement of these components. Components that tend to run very hot (large BIPOLAR or NMOS devices) should be placed on the Interface Board in areas away from the two CMOS gate arrays on the co-processor adapter card whenever possible. These critical placement areas will differ slightly depending on which co-processor adapter card the Interface Board will reside on. It should be noted that the gate array case temperatures should not exceed 85 degrees C.
Under normal operation, the components of the co-processor adapter card under the Interface Board have cool-to-moderate case temperatures, and should not cause appreciable heat to be transferred to the Interface Board components.
This chapter contains the Raw Card Dimensions and Specifications for an Interface Board
The distance between the Interface Board and the co-processor adapter varies, depending upon which co-processor adapter is used. This separation is 12.7 mm (0.500 in.) for the Portmaster Adapter/A card, and it is 10.1 mm (0.400 in.) for the Multiport Adapter, Model II card.
When designing the layout of components for an Interface Board, the existence of co-processor adapter card components on the adjacent mating area must be taken into account.
Figure 38 shows the raw card dimensions and the component height restrictions for the Interface Board. Refer to Figure 39 for applicable notes.
Figure 38. Interface Board Dimension Diagram
| 77.47 / 3.05 |
|<----------------------------------------------------------->|
| | 75.7 / 2.98 |
| |<--------------------------------------------------------->|
| || 66.04 / 2.6 | |
| ||<------------------------------------------------->| |
| || | 38.87 / 1.53 | |
| || |<----------------------|----->|
| || | 38.1 / 1.5 | | | |
| || |<--------------|-------------------->| | |
| || | | | | |
| || | | |<|----->|--- 15.24 / 0.6
| || | | @3.17 / .125 --+ | | | | |
| || | | Tooling Hole \ | |->| |<|--- 2.54 (TYP) / 0.1
| || | | (Note Required) \ | | | | |
| || | | \ | |--|>| |<-- (5X) 2.04 / 0.08
| || | | \| | | | |
----------------------------------+====================================================\========+
^ | || | | |\| | | |
| ------|-||-----------|---------------|---------------------|-O | | |
| ^ | || | | | | | |
| ---------------------------|---|1o|o o o o o o|o o o o o o o o|o o o o o o o o o o o|o o o o |
| ^ | | | | | | |
| | ------------------------|---|1o|o o o o o o|o o o o o o o o|o o o o o o o o o o o|o o o o |
| | ^ ---------------------|---|2o|o o o o o o|o o o o o o o o|o o o o o o o o o o o|o o o o |
| | | ^ | | | | | | |
| | | | ------------------|---|1o|o o o o o o|o o o o o o o o|o o o o o o o o o o o|o o o o |
| | | | ^ ---------------|---|2o|o o o o o o|o o o o o o o o|o o o o o o o o o o o|o o o o-|-- @(150X) 1.0 / 0.039
| | | | | ^ | | | | | | |
| | | | | | | | | | /-\ | |
| | | | | | | | | | @4.0 / .157---O|--------------------|--------|-----------------------
| | | | | | | | | | \-/ | | ^
| | | | | | | | | | \ | | |
| | | | | | | | | | \ | | |
| | | | | | | | | | \ | | |
| | | | | | | | | | @6.6 + 0.25 | | |
| | | | | | | | | | 0.260 | | |
| | | | | | | | | | (2) | | 125.65 / 4.947 ---+
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | | | | |
| | | | | | | | | +=====================================+--------|--------- |
| | | | | | | | | | | | ^ |
163.95 | | | | | | 116.84 | | | | | | | |
/ 6.455 -----+ | | | | | / 4.6 ---+ | | | | | | |
| | | | | | | | | | | | | |
(30X) 147.44 | | | | | | | | | | | | | |
/ 5.805 -----|--+ | | | | | | | | | | | |
| | | | | | | | | | | | | |
(30X) 142.36 | | | | | | | | | | | | | |
/ 5.605 -----|--|--+ | | | | | | | (9) | | | |
| | | | | | | | | | | | +- 38.1 / 1.5 |
(30X) 139.82 | | | | | | | | | | | | | |
/ 5.505 -----|--|--|--+ | | | | | | | | | |
| | | | | | | | | | | | | |
(30X) 134.74 | | | | | | | | | | | | | |
/ 5.305 -----|--|--|--|--+ | | | | | | | | |
| | | | | | | | | +@3.17 | | | | |
(30X) 132.2 | | | | | | | | | / .125 | | | | |
/ 5.205 -----|--|--|--|--|--+ | | |/ | | | | |
| | | | | | ------------V---|==/ | | | V |
| | | | | | ^ -------------| O|(6) +=====================================+--------|------------------- |
44.69 / 1.76 -|--|--|--|--|--|--+ ^ ----------|==+ | ^ |
| | | | | | | | ^ | || (6)+=|---------------- | |
| | | | | | | | | | || +-- Area indicated Free of | | ^ | |
39.69 / 1.563-|--|--|--|--|--|--|--+ | | || / Components on Base Card | | 38.1 / 1.5 --+ | |
| | | | | | | | | -------|====+ | |40.76 / 1.605-|--+ |
| | | | | | | | | ^ | || | +--@(2X) 1.0 / 0.039 (7) | | | | |
34.69 / 1.365-|--|--|--|--|--|--|--|--+ | | || | / (25X) 10.28 / 0.405 -----|-|-----+ | | |
| | | | | | | | | | ----|====+/ (28X) 12.82 / 0.505 -----|-|--+ | | | |
| | | | | | | | | | ^ | || / | | | | | | | |
27.6 / 1.086 -|--|--|--|--|--|--|--|--|--+ | | ||O|o o o o o o o o o o o o o o o o o o o o o5o4o3o2o1o O-|-|---- | | | | | |
| | | | | | | | | | | | || ||o o o o o o o o o o o o o o o o o o o o o o o o o|---|-|--^---- V | | | |
14.9 / 0.586 -|--|--|--|--|--|--|--|--|--|--+ | ||O|| o o o o o o o o o o o o o o o o o o o o o o o o | O-|-|--|--^---- V | | |
| | | | | | | | | | | | |/|||o o o o o o o o o o o o o o o o o o o o o o o o o|-|-|-|--|--|--|---- | | |
V V V V V V V V V V V | /|||100 ^ || | | | V V | | V V V
-----------------------------------------------+/=============|==============================================+----------------------
/ ||||| | || | | |\ ^ ^
/ ||||| +@(100X) 0.840 +/-0.05 || | | | \ | | (25X)
/ ||||| 0.033 +/-.002 || | | | \ | +-5.20 / 0.205
@(2X) 3.18 +/- 0.076 --+ ||||| || | | | \ |
.125 +/- 0.003 ||||| 2.54 / 0.100 ----||-|>| |< \ | (26X)
(3) (5) ||||| || | | \ +-- 7.74 / 0.305
||||| (2X) 7.37 / 0.290 ----||-|<->| \
||||| || | \
||||| 14.11 / 0.556 ----||<--->| \
||||| || | \
||||| 0.95 (TYP) / 0.038 --->||<-- | \ (0,0) ORIGIN
||||| 61.74 / 2.431 | +-------------
|||||<----------------------------------------------------->|
|||| 67.27 / 2.648 |
||||<------------------------------------------------------>|
||| (2X) 68.48 / 2.696 |
|||<------------------------------------------------------->|
|| 71.47 / 2.814 |
||<-------------------------------------------------------->|
| 74.47 / 2.932 |
|<--------------------------------------------------------->|
(1) Card is 4S.2P LAY UP with the overall dimention ---> 1.570 +/- 0.127
0.062 +/- 0.005
Figure 39. Notes for Dimension Diagram and Assembly Diagram
NOTES:
(1) Dimension is critical to Function
(2) Areas indicated to be free of traces and components. Solder Mask not
permitted in these areas
(3) The plated thru "D" shell commector mounting holes are connected to
the AC ground in the card. The AC ground must be separated from the
DC ground by 0.6 mm (0.024 in) in the card from both safety and EMC
considerations. 0.250 in square solder pad around these holes.
4 Tolerances shown to include all of the individual process tolerances
and are to be non-cumulative.
(5) Align artwork with centerline of this feature.
(6) This area is to be free of components
(7) Plated thru "D" shell connector grounding pins are connected to the AC
ground in the card.
8 Maximum component height 0.200 inch for A.T. and PS/2 interface boards.
(9) Maximum conponent height 0.165 inch in this area (A.T. only)
10 Maximum component height 0.250 inch for PS.2 interface boards.
11 Non-wettable components, NONE
The IBM-supplied customer-level and advanced-level diagnostics will not function properly with a custom IB installed on the co-processor adapter. If a developer wishes to use IBM-supplied diagnostics, these diagnostics should be run on the Adapter itself, with no IB installed. When diagnostics are performed in this manner, the Adapter functionally tests all of its functions, including DUSCC0, DUSCC1, and both CIOs; however, the integrity of the IB interface is not tested.
A specific application should be written for the Interface Board to test the IB interface and all of the functions on the Interface Board.
Last modified: March 25, 1999