Technical Reference
Second Edition (April 1995)
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Avis de conformité aux normes du ministère des Communications du Canada
Cet équipement ne dépasse pas les limites de Classe A d'émission de bruits radioélectriques pour les appareils numériques, telles que prescrites par le Règlement sur le brouillage radioélectrique établi par le ministère des Communications du Canada. L'exploitation faite en milieu résidentiel peut entraîner le brouillage des réceptions radio et télé, ce qui obligerait le propriétaire ou l'opérateur à prendre les dispositions nécessaires pour en éliminer les causes.
References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates.
Any reference to an IBM licensed program or other IBM product in this publication is not intended to state or imply that only IBM's program or other product may be used.
The following terms, DENOTED BY A PLUS SIGN (+) the first time they are used in this publication, are trademarks or service marks of IBM Corporation in the United States and/or other countries:
IBM Micro Channel OS/2 Operating System/2 PS/2 Portmaster
The following terms, DENOTED BY A DOUBLE PLUS SIGN (++) the first time they are used in this publication, are trademarks of other companies as follows:
This publication contains technical reference information for the IBM+ Realtime Co-Processor Portmaster+ Adapter/A.
Note:
Throughout this publication, the general term co-processor adapter is used to designate the feature card named above.
The objectives of this publication are to:
Note:
Firmware information can be found in the IBM Realtime Interface Co-Processor Firmware Technical Reference.
The information in this book is both introductory and for reference use. It is intended for hardware and software designers, programmers, engineers, and anyone with a knowledge of electronics and programming who wishes to understand the use and operation of the co-processor adapter.
It is assumed that the reader is familiar with the co-processor adapter, as well as the system unit, the applications in use, and programming. Therefore, only terms that may have special meaning are explained in this book.
The information in this book is organized as follows:
This publication contains instructions for installing and setting up the Realtime Interface Co-Processor Portmaster Adapter/A, as well as the optional interface boards and cables.
This library is used to isolate and repair a faulty field-replaceable unit. It provides instructions for problem isolation to help identify a faulty unit. Removal and replacement procedures are presented to complete the repair.
This publication describes the programmer interfaces to the Realtime Control Microcode.
This publication provides information necessary to interface the co-processor adapter through the system unit DOS. It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode DOS Support software.
This publication is a productivity aid that provides the system developer with a variety of services to ease the writing of systems applications for the Realtime Interface Co-Processor family of adapters. It includes numerous task, event, resource, and communications services that allow the system developer to concentrate on the application instead of the system.
This publication provides information necessary to interface the co-processor adapter through the system unit Operating System/2+ (OS/2+). It describes all functions and capabilities, as well as installation, of the Realtime Control Microcode OS/2 Support software.
This publication is a productivity aid that allows programmers to develop code for the co-processor adapter in the C programming language. It explains the C interface routines and the method of compiling and linking C tasks for the co-processor adapter.
One or more of the following publications might be needed for reference when using this book.
This chapter provides a brief description of the Realtime Interface Co-Processor Portmaster Adapter/A, and serves as a quick reference guide to the major hardware components, electrical interfaces, and physical interfaces. The information in this chapter is divided into two main topics:
The IBM Realtime Interface Co-Processor Portmaster Adapter/A is a Micro Channel+ bus master option for use in the following IBM computer models:
This adapter card occupies just one expansion slot and can be installed in any available slot. It has the facilities to support applications such as communications control, data/protocol conversion, and nonstandard device interfacing that require a realtime, multitasking environment.
Optional interface boards plug onto the co-processor adapter card. The interface boards contain up to eight serial communication ports, each capable of operating in duplex, independent of each other. Each of the ports can support various electrical interfaces and protocols.
The co-processor adapter card provides serial communications capability, without degrading the performance of the system unit. This card serves as an input and output adapter for the system unit. In addition, the card is programmable, using a self-contained 80C186 microprocessor to perform on-board processing.
Through the use of optional interface boards, the co-processor adapter can support various communications protocols such as: RS-232-D, RS-422-A, X.21, V.35, and so forth.
Simultaneous duplex communications can be supported on up to eight ports at data rates of 64K baud, or duplex on a single port at a data rate of up to 2.048M baud.
The co-processor adapter card provides processing power through the on-board 80C186 processor. This enables the system unit to off load most processing associated with communications.
Typical tasks for which the processor can be programmed include the following:
The co-processor adapter provides the following software support functions:
The co-processor adapter card has 16 DMA channels dedicated to the transmit and the receive function of each of eight ports. In addition, two DMA channels are assigned to on-card memory-to-memory transfers.
This section lists major hardware components and physical interfaces on the co-processor adapter. These components are described in detail in later chapters and appendixes.
This chapter describes the details of individual components on the co-processor adapter. Each major component is described in terms of its function, physical characteristics, and special features. For those hardware components that are programmable, programming considerations are provided or referenced.
The adapter-related components described in this chapter include:
The following block diagram shows the interaction of the adapter-related components.
+---+
| M |
| i |
| c | +-----------+ RAM Data +-----+
| r | +---+ | CMOS |<------------>| |
| o | Data (16) | B | |Gate Array | RAM Address | RAM |
| |<---------------->| u |<------->| |<------------>| |
| C | Address (32) | f | | RAM | RAM Control | |
| h |<---------------->| f |<------->|Controller/|<------------>+-----+
| a | Ctrl/Arbitration| e | |Bus Master | 3
| n |<---------------->| r |<------->| Interface | 2 +---+ D
| n | +---+ +-----------+ 1 +--+-+ | a
| e | ^ ^ 0 +-+--+ | |<-+ t
| l | | | A/D 0-7 +-+--+ | | | | a
+---+ | | +------------->| | | +-+ |
| | | +------->|DUSCC +-+ | &
+---+ Control | | | | +----<+ +-+ |
| 8 |<-------------+--------------------+ | | | | +----+ | M
| 0 | | | | | | | o
| C | Address/Data|(16) | | | | | d
| 1 |<-------------|--+----------------------+ | | | 1 | e
| 8 | | | | | | 0 +----+ | m
| 6 | HoldAck | | | | | +-+--+ | |
| |<----------+ | | +-----|--|---->| | |---+ | C
| C | | | | | +--|---->|CIO | | | | t
| P | Hold | | | A/D 0-15 +----+---+ | | | +-+ | | r
| U |<--------+ | | | | Buffer | | | +----+ | | l
+---+ | | | | +--------+ | | V V
| | | | | | | +-----+
| | | +----+-------------------+-+ | | | 8 |
| V V V | ^ Data | | | |
+-+---------+ | +---+ +---+---+ | | | P |
| CMOS | | | L | Address| PROM | | | | o |
|Gate Array | +->| A +------->| | | | | r |
| | | T | +-------+ | | | t |
| DMA/ | +---+ DUSCC Ctrl | | | |
|Peripheral +------------------------------+ | | I |
| Interface | DMA Request (16) | | / |
| |<--------------------------------+ | F |
+-----------+ +-----+
Notes:
Random access memory (RAM) on the co-processor adapter provides 512KB, 1MB, or 2MB of on-board read/write storage. For the 2MB option, memory address translation is used to map the 2MB of physical storage into the 80C186 co-processor's 1MB address space.
The RAM controller and bus master interface chip serves as the dual-ported RAM controller arbitrating RAM requests from the 80C186 co-processor and the system unit processor. It also provides other RAM support features including:
The RAM controller and bus master interface chip guarantees the RAM cycle time to be 200 nanoseconds, which provides a maximum data rate of 10MB per second from the RAM. Neither processor can access the RAM this fast; however, each processor "holds" the RAM for only 200 nanoseconds, then "releases" it. The other processor then is allowed access, if needed.
Self-diagnostics in the on-board PROM test the RAM for size, addressability, and parity. These diagnostic test modules can be called by user tasks on the co-processor adapter.
Dynamic RAM SIPS (256KB X 18, 256KB X 36, and 512KB X 36) with an 85-nanosecond access time are used on this adapter.
Information on all configurations is found in the IBM Realtime Interface Co-Processor Portmaster Adapter/A Guide to Operations and the IBM Realtime Interface Co-Processor Portmaster Adapter/A and Multiport Adapter, Model 2 Hardware Maintenance Library.
The 80C186 processor can directly access 1MB of memory using its 20 address lines. A translate table, stored in a 64 x 9 high-speed static RAM in the RAM controller and bus master interface chip, allows the 80C186 to access up to 2MB of dynamic RAM. The 2MB region is divided into 128 blocks of 16KB. While all 128 blocks can be accessed, only 64 of the 128 blocks can be accessed at any given time, as the mapping must be done within a 1MB address range.
Figure 1. shows a block diagram of the translate table.
Figure 1. Translate Table Block Diagram
Logical Physical
Address Address
+-----------+
A14 ----->| | -----> TA14
A15 ----->| | -----> TA15
A16 ----->| 64 X 9 | -----> TA16
A17 ----->| High-Speed| -----> TA17
A18 ----->| RAM | -----> TA18
A19 ----->| | -----> TA19
| | -----> TA20
Read Enable -->| | -----> Write Protect bit
Write Enable -->| | -----> Read/Write Protect bit
+-----------+
In operational mode, the upper six 80C186 physical address lines (A14-A19) are decoded to point to 1 of the 64 entries in the translate table. These lines are replaced on the address bus by translated address lines A14-A20 (TA14-TA20). The seven translated address lines (TA14-TA20) then point to any 1 of the 128 blocks of 16KB, providing 2MB of logical address space. Address lines A0-A13 are needed to access any byte within a 16KB block, but are not used for translate table access. The final translated address is achieved by concatenating TA20-TA14 with A13-A0. The translate address generation process is shown in Figure 2..
Figure 2. Translate Address Generation
Translate Table RAM
|TA|TA|TA|TA|TA|TA|TA|R/|WP| 1 Meg
|20|19|18|17|16|15|14|WP| | +---------+
+--------------------------+ | 16KB |
111111| | +---------+
+---+ +--+--+--+--+--+--+--+--+--+ | : |
I/O 6 | | | | +---------+
Address ->| | 6 +--+--+--+--+--+--+--+--+--+ +----->| 16KB |
|MUX| ---->| |--|---+ +---------+
80C186 6 | | +--+--+--+--+--+--+--+--+--+ | |
A19-A14 -->| | | | | | 1 Meg
| | +--+--+--+--+--+--+--+--+--+ | | +---------+
+---+ | |--|-+ +->| 16KB |
+--+--+--+--+--+--+--+--+--+ | | +---------+
| |--+ +--->| : |
+--+--+--+--+--+--+--+--+--+ +---------+
000000| |-------->| 16KB |
+--------------------------+ +---------+
^
80C186 |
A13-A0 --------------------------------------------------------+
Two protection bits, a write protect (WP), and a read/write protect (R/WP), are provided in each entry of the translate table. These bits can be used to protect the integrity of the data stored in the 16KB blocks pointed to by the entries in the translate table. The use of these bits is detailed in "Protection Scheme". The protection bits can be disabled by an I/O write to the co-processor adapter TTPROTOFF register and re-enabled by an I/O write to the co-processor adapter TTPROTON register. The use of these registers also is described in "Protection Scheme", and is detailed in "Translate Table Protection On Register (TTPROTON)" and "Translate Table Protection Off Register (TTPROTOFF)".
A typical translate table entry is illustrated in Figure 3.. The unused bits must be set to 0s.
Figure 3. Translate Table Entry
+--------+----+----+----+----+----+----+----+----+----+
| D15-D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+----+---+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+--+-+
| | | | | | | | | |
| | | | | | | | | +--- WP
| | | | | | | | +-------- R/WP
| | | | | | | +------------- TA14
| | | | | | +------------------ TA15
| | | | | +----------------------- TA16
| | | | +---------------------------- TA17
| | | +--------------------------------- TA18
| | +-------------------------------------- TA19
| +------------------------------------------- TA20
+-------------------------------------------------- RSVD
Data can be written to or read from the translate table
using 80C186 I/O addresses.
All registers are 16-bit R/W registers and are mapped to
the I/O addresses shown in Figure 4..
Figure 4. Translate Table Map
+-----------------+-------------+ | Translate Table | I/O Address | | Registers | (hex) | +-----------------+-------------+ | 0 - 7 | C000 - C00E | +-----------------+-------------+ | 8 - 15 | C010 - C01E | +-----------------+-------------+ | 16 - 23 | C020 - C02E | +-----------------+-------------+ | 24 - 31 | C030 - C03E | +-----------------+-------------+ | 32 - 39 | C040 - C04E | +-----------------+-------------+ | 40 - 47 | C050 - C05E | +-----------------+-------------+ | 48 - 55 | C060 - C06E | +-----------------+-------------+ | 56 - 63 | C070 - C07E | +-----------------+-------------+
The upper four entries of the translate table, where the A19-A14 address lines may equal 111111, 111110, 111101, or 111100, are special cases and are controlled by programming the 80C186 Upper Memory Chip Select (UMCS) register.
As described in "RAM/PROM Memory Map", the PROM area is 64KB, which includes 32KB of usable PROM and 32KB reserved for future use. The lower boundary of this area is 0F0000h.
The co-processor adapter uses the UMCS register to establish the lower boundary of the area set aside for PROM. Note that all addresses in this range have A19-A16 set to 1111. When an address within this bound is accessed, the UMCS line will go active, which causes PROM to be selected rather than any entry in the translate table. Some of the upper four entries of the translate table can be used if the UMCS register is programmed with a value that allocates less than 64KB to the PROM area.
For example, if the UMCS register is programmed to specify a PROM area that does not extend to 0F0000h, the four upper-order entries of the translate table can be accessed until the value of the logical address falls into the area set aside for PROM. The advantage of using the programmability of the UMCS register is the use of more entries of the translate table to point to 16KB blocks of dynamic RAM.
There is one case in operational mode where the translate table is not used. The translate table is bypassed on DMA/peripheral interface chip DMA accesses to the dynamic RAM. In this case, the DMA address provides all 21 address bits required to access any area within the 2MB range.
The translate table is used on 80C186 DMA accesses to the dynamic RAM. This table also is used for options of installed dynamic RAM on the co-processor adapter (that is, 512KB, 1MB, and 2MB). For 2MB of installed memory, the translate table allows the 80C186 with only 20 address lines (1MB range) to access any byte within a 2MB address space.
The write protect (WP) bit, when set to 1, forces a non-maskable interrupt (NMI) back to the 80C186 on a write access to any byte within the block pointed to by TA14-TA20. Read access is not affected. The read/write protect (RWP) bit, when set to 1, forces a non-maskable interrupt (NMI) back to the 80C186 on any access to any byte within the block pointed to by TA14-TA20. In either case, a bit is set in the NMI Status Register to indicate that a translate table violation was the source of an interrupt. This bit does not differentiate between the two sources of translate table NMIs. The software must determine the exact cause of the interrupt. Once an NMI is generated, subsequent accesses in violation of protected blocks will not generate NMIs unless the previous NMI has been cleared by a read of the NMI Status Register.
For a translate table NMI, the logical address that pointed to the translate table is latched in the Parity Register. Note that a translate-table write-protect violation blocks the write to the dynamic RAM and generates an NMI, whereas a read-protect violation only generates an NMI, and allows the read operation to proceed.
Figure 5. It also shows how the read/write protect (R/WP) bit is ANDed with the 80C186 status line (-S2) to disable a write access and to generate an NMI to any specified 16KB block. This scheme, however, does not prevent two entries in the translate table from pointing to the same 16KB block, where one entry has a protect bit set and the other does not.
This figure also shows how the Translate Table Protection On and Off (TTPROTON and TTPROTOFF) bits can be used to override the setting of the individual write (WP) and read/write protect (R/WP) bits.
Figure 5. Write and Read/Write Protect Scheme
Logical Physical
Address Address
+-----------+
A14 ----->| | -----> TA14
A15 ----->| | -----> TA15
A16 ----->| 64 x 9 | -----> TA16
A17 ----->| High-Speed| -----> TA17
A18 ----->| RAM | -----> TA18
A19 ----->| | -----> TA19
| | -----> TA20
Read En -->| | ---+-> Write Protect (WP) bit
Write En -->| | -+-|-> Read/Write Protect (R/WP) bit
+-----------+ | |
| |
| | +-----+
| +---->| |
80C186 Write (-WR) -------------|------>| AND +---+
TTPROTON --------------------+-|------>| | |
TTPROTOFF ------------------+-|-|------>| | | +-----+
| | | +-----+ | | |
| | | +->| OR +---> NMI
| | | +-----+ +->| |
| | +------>| | | | |
80C186 Read/Write Status ---|-|-------->| AND | | +-----+
(-S2) | +-------->| +---+
+---------->| |
+-----+
Diagnostics are provided for the RAM and the translate table. During diagnostic testing, various read and write tests are performed to functionally check the operation of the translate table write protect and read/write protect bits, as well as the protection override functions of the TTPROTON and the TTPROTOFF registers. The tests are performed with the translate table NMIs masked on and off in the NMIMASK register.
The translate table functional test is run during POST, and cannot be called by a user task.
As shown in the "RAM/PROM Memory Map", 64KB of 80C186 memory (F0000h-FFFFFh) are available for the on-board PROM. Of this 64KB, the upper 32KB are usable, and the lower 32KB are reserved for future use.
The 80C186 upper memory chip select register establishes the lower boundary (F8000h) of the area set aside for usable PROM. Approximately 20KB of usable PROM are occupied by microcode, consisting of a Bootstrap Loader, a set of Diagnostic Support Routines, and a set of PROM Services. On-board PROM code cannot be accessed by the system unit.
Two 27C256 chips (150-nanosecond access time) provide the 64KB of co-processor adapter PROM.
Power-on diagnostics perform a checksum verification on PROM, among other diagnostic tests. A checksum test also can be performed on PROM by a user task calling the checksum diagnostic routine.
A typical RAM/PROM memory map is shown here.
Address
(hex) Bytes
- - - - - +------------+ - - - - -
1FFFFFh | | 2048KB
| |
|Bankswitched|
| RAM |
| |
100000h | |
- - - - - +------------+ - - - - -
FFFFFh | Usable | 1024KB
| PROM |
F8000h | (32K) |
- - - - - +------------+ - - - - -
F7FFFh | Reserved | 992KB
| PROM |
F0000h | (32K) |
- - - - - +------------+ - - - - -
EFFFFh | | 960KB
| |
| RAM |
| |
00000h | |
- - - - - +------------+ - - - - -
Note:
The 80C186 microprocessor can address only 1MB of physical memory. Memory address translation must be used to access any physical memory that is above 1MB.
The Intel 80C186 is the microprocessor on the co-processor adapter. Its primary functions are to:
The 80C186 microprocessor has the following physical characteristics:
Standard programming of the 80C186 is described in detail in the Intel user's documentation and is not included here. However, guidelines are provided in this subsection for certain features that:
Five possible interrupt lines exist on the 80C186: NMI, INT0, INT1, INT2, and INT3. The definitions and pin numbers of the interrupt lines are shown in Table 3.
Table 3. 80C186 Interrupts
+-----------------+-----------------+-----------------------------------+ | Signal Name | Signal Pin # | Description and Assignment | +-----------------+-----------------+-----------------------------------+ | NMI | 46 | Non-maskable interrupt. (Used to | | | | report various error conditions | | | | such as RAM parity error, watchdog| | | | NMI command, I/O channel check, | | | | channel reset, bankswitch memory | | | | write-protect or read/write | | | | protect error, duagbistic address | | | | compare, and no-card-selected | | | | feedback return. | +-----------------+-----------------+-----------------------------------+ | INT0 | 45 | Non-vectored interrupt. Generated | | | | by any interrupt source associated| | | | with the system unit; INTCOM, Bus | | | | Master CH. A 2-level status | | | | register identifies the source of | | | | the interrupt. | +-----------------+-----------------+-----------------------------------+ | INT1 | 44 | Vectored interrupt. DUSCC, CIO, | | | | and DMAINT interrupts. | +-----------------+-----------------+-----------------------------------+ | INT2 | 42 | Not used. | +-----------------+-----------------+-----------------------------------+ | INT3 | 41 | Interrupt acknowledge for DUSCC, | | | | CIO, and 80C186 DMAs. | +-----------------+-----------------+-----------------------------------+The 80C186 uses internal interrupt vectors for NMI (non-maskable interrupts) and INT0. In the case of INT1, the DUSCC, CIO, or DMA/peripheral interface chip provides the interrupt vector. Logic within the DMA/peripheral interface chip decides which device supplies the vector during the interrupt acknowledgement cycle. The interrupt priority is as follows:
Highest DUSCC0 - Supports ports 0 and 1
. DUSCC1 - Supports ports 2 and 3
. DUSCC2 - Supports ports 4 and 5
. DUSCC3 - Supports ports 6 and 7
. CIO0 - Supports ports 0 and 1
. CIO1 - Supports ports 2 and 3
. DMAINT0 - Supports DMA interrupt 0
. .
. .
. .
Lowest DMAINT15 - Supports DMA interrupt 15
The only thing a task should ever do to the Interrupt Controller is to issue a non-specific End Of Interrupt (EOI) command. Any other command or change could lead to unpredictable results.
After any hardware interrupt, this register must be written to enable more interrupts on the priority level of the last interrupt, or on a lower priority level. The only EOI command that should be issued is the non-specific EOI. This is done by writing 8000h to I/0 port FF22h.
Example:
MOV AX,8000h ;Set data value for non-specific EOI MOV DX,0FF22h ;Set I/O address OUT DX,AX ;Issue EOI
Figure 6. provides a summary of the 80C186
Interrupt Controller Registers and their respective
offset addresses.
All registers are read/write, unless otherwise specified by the
80C186 manual. Only level-sensitive interrupts are supported by
the co-processor adapter.
Figure 6. Interrupt Controller Register Addresses
Register Offset
Address
+--------------------------------+
| INT3 Control Register | FF3Eh
+--------------------------------+
| INT2 Control Register | FF3Ch
+--------------------------------+
| INT1 Control Register | FF3Ah
+--------------------------------+
| INT0 Control Register | FF38h
+--------------------------------+
| DMA 1 Control Register | FF36h
+--------------------------------+
| DMA 0 Control Register | FF34h
+--------------------------------+
| Timer Control Register | FF32h
+--------------------------------+
| Interrupt Status Register | FF30h
+--------------------------------+
| Interrupt Request Register | FF2Eh
+--------------------------------+
| In-Service Register | FF2Ch
+--------------------------------+
| Priority Mask Register | FF2Ah
+--------------------------------+
| Mask Register | FF28h
+--------------------------------+
| Poll Status Register | FF26h
+--------------------------------+
| Poll Register | FF24h
+--------------------------------+
| EOI Register | FF22h
+--------------------------------+
The 80C186 can be programmed to provide ready or wait state generation for both (or either) memory or I/O peripherals. Memory (PROM and RAM) is programmed to insert zero wait states, and use an external ready signal, which is controlled by the RAM controller and bus master interface chip. Peripherals are programmed for zero wait states, and the external ready signal also is accepted. The wait bits are located in bits 2, 1, and 0 of the MPCS, UMCS, and PACS registers.
Table 4. Chip-Select Register Addresses
+--------------------+--------------------+------------------------------+ | Register | I/O Address | Register Type | +--------------------+--------------------+------------------------------+ | MMCS | FFA6h | Mid-Range Memory Chip-Select | +--------------------+--------------------+------------------------------+ | LMCS | FFA2h | Lower-Memory Chip-Select | +--------------------+--------------------+------------------------------+ | UMCS | FFA0h | Upper-Memory Chip-Select | +--------------------+--------------------+------------------------------+ | PACS | FFA4h | Peripheral Chip-Select | +--------------------+--------------------+------------------------------+ | MPCS | FFA8h | Peripheral Chip-Select | +--------------------+--------------------+------------------------------+
The three 80C186 timers are reserved for use by the Realtime Control Microcode.
Refer to the IBM Realtime Interface Co-Processor Firmware
Technical Reference for further details.
The timer I/O addresses are shown in Figure 7..
Figure 7. Timer I/O Addresses
+-------------------+-----------------------------+ | | Register Address | | Control Register +---------+---------+---------+ | | Timer 0 | Timer 1 | Timer 2 | +-------------------+---------+---------+---------+ | | | | | | Mode/control word | FF56h | FF5Eh | FF66h | | | | | | | Max count B | FF54h | FF5Ch | -- | | | | | | | Max count A | FF52h | FF5Ah | FF62h | | | | | | | Count register | FF50h | FF58h | FF60h | | | | | | +-------------------+---------+---------+---------+
The 80C186 Peripheral Control Block is set up by the power-on diagnostics. It is located in I/O space at address FF00h-FFFFh. The only areas of the Peripheral Control Block that can be modified are the DMA descriptors and interrupt controller registers. Modifying anything else will cause unpredictable results.
The DMA registers are located at FFC0h-FFCAh for channel 0 and at FFD0h-FFDAh for channel 1 as shown in Figure 8.. (Refer to Intel 80C186 publications for a detailed description of the DMA registers.) PROM Services can be used to program the DMA such that it should not be necessary to use the DMA registers directly.
The internal DMAs should be used mainly for on-card memory-to-memory
moves.
They can be used for memory-to-I/O transfers, but only to I/O registers.
The external request lines are not connected to any device.
Therefore, these channels can operate only in the unsynchronized mode.
Figure 8. DMA Register Locations
+---------------------+------------------------+ | | Register Address (hex) | | Register Name +-----------+------------+ | | Channel 0 | Channel 1 | +---------------------+-----------+------------+ | Control Word | FFCA | FFDA | | Transfer Count | FFC8 | FFD8 | | Destination Pointer | FFC6 | FFD6 | | (upper 4 bits) | | | | Destination Pointer | FFC4 | FFD4 | | Source Pointer | FFC2 | FFD2 | | (upper 4 bits) | | | | Source Pointer | FFC0 | FFD0 | +---------------------+-----------+------------+
Other details of the 80C186 microprocessor and its programming can be found in the Intel iAPX 86/88, 186/188 User's Manual, 1983, or the Intel Embedded Controller Handbook, 1987.
The I/O map of the 80C186 addressable registers is shown in Table 5.. Detailed information for each register is located on the referenced page.
Three different types of reset conditions affect the co-processor adapter registers:
Table 5. 80C186 Addressable Registers
+----------------------+------------------------+-------------------------+ | Register/Command | 80C186 Address (hex) | Detailed Information | | | | (Page #) | +----------------------+------------------------+-------------------------+ | BMCH | 20-2E | the appropriate section | +----------------------+------------------------+-------------------------+ | BMCH1RESET | A0 | the appropriate section | +----------------------+------------------------+-------------------------+ | CIO0 | 180-1FF | the appropriate section | +----------------------+------------------------+-------------------------+ | CIO1 | 500-5FF | the appropriate section | +----------------------+------------------------+-------------------------+ | CRDIDREG | 88 | the appropriate section | +----------------------+------------------------+-------------------------+ | CPUPG | 14 or 5E | the appropriate section | +----------------------+------------------------+-------------------------+ | DB ID | 86 | the appropriate section | +----------------------+------------------------+-------------------------+ | DB I/O CS | F000-FFFF | the appropriate section | +----------------------+------------------------+-------------------------+ | DB ROS CS | E000-EFFF | the appropriate section | +----------------------+------------------------+-------------------------+ | DMAASSIGN | 8212 | the appropriate section | +----------------------+------------------------+-------------------------+ | DMADISABLE | 8214 | the appropriate section | +----------------------+------------------------+-------------------------+ | DMAEOI | 3220-3225 | the appropriate section | +----------------------+------------------------+-------------------------+ | DMAPG | 40-5C | the appropriate section | +----------------------+------------------------+-------------------------+ | DMASSO -15 | 8000-81FE | the appropriate section | +----------------------+------------------------+-------------------------+ | DMASTAT | 8200-820F | the appropriate section | +----------------------+------------------------+-------------------------+ | DMAVECTOR | 8210 | the appropriate section | +----------------------+------------------------+-------------------------+ | DUSCC0 | 1800-18FF | the appropriate section | +----------------------+------------------------+-------------------------+ | DUSCC1 | 1900-19FF | the appropriate section | +----------------------+------------------------+-------------------------+ | DUSCC2 | 1A00-1AFF | the appropriate section | +----------------------+------------------------+-------------------------+ | DUSCC3 | 1B00-1BFF | the appropriate section | +----------------------+------------------------+-------------------------+ | ENREG | 800 | the appropriate section | +----------------------+------------------------+-------------------------+ | GAID | 18 | the appropriate section | +----------------------+------------------------+-------------------------+ | INITREG0, 1, 3 | 04, 06, 1A | the appropriate section | +----------------------+------------------------+-------------------------+ | INTIDREG | 92 | the appropriate section | +----------------------+------------------------+-------------------------+ | INTOSTAT | 90 | the appropriate section | +----------------------+------------------------+-------------------------+ | IOCHCK | 94 | the appropriate section | +----------------------+------------------------+-------------------------+ | LOCREG0, 1 | 00, 02 | the appropriate section | +----------------------+------------------------+-------------------------+ | NMIMASK | 08 | the appropriate section | +----------------------+------------------------+-------------------------+ | NMISTAT | 0A | the appropriate section | +----------------------+------------------------+-------------------------+ | PCCSTAT | 8A | the appropriate section | +----------------------+------------------------+-------------------------+ | PCPAR0, 1, 2 | 96, 98, 9A | the appropriate section | +----------------------+------------------------+-------------------------+ | PESTAT | 8C | the appropriate section | +----------------------+------------------------+-------------------------+ | PROCSYNC | 8E | the appropriate section | +----------------------+------------------------+-------------------------+ | RICPAR0, 1, 2 | 0C, 0E, 10 | the appropriate section | +----------------------+------------------------+-------------------------+ | SIMMCONFIG | 802 | the appropriate section | +----------------------+------------------------+-------------------------+ | TREG | 12 or 16 | the appropriate section | +----------------------+------------------------+-------------------------+ | TRAN0-63 | C000-C07E | reference #1 | +----------------------+------------------------+-------------------------+ | TTPROTON | 9C | the appropriate section | +----------------------+------------------------+-------------------------+ | TTPROTOFF | 9E | the appropriate section | +----------------------+------------------------+-------------------------+
This co-processor adapter read/write register provides eight control bits that can be defined by the specific interface board. The co-processor adapter uses these bits to control the selection of either DTE or DCE clocking options.
I/O Addresses
-------------
Co-Processor Adapter
ENREG = 0800h
System Unit = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ ENREG
| | | | | | | |
| | | | | | | +----- +DCE/-DTE 0
| | | | | | +-------- +DCE/-DTE 1
| | | | | +----------- +DCE/-DTE 2
| | | | +-------------- +DCE/-DTE 3
| | | +----------------- +DCE/-DTE 4
| | +-------------------- +DCE/-DTE 5
| +----------------------- +DCE/-DTE 6
+-------------------------- +DCE/-DTE 7
Bits 0-7
These direct I/O bits are wired to the interface board and are defined
by the specific interface board. The
co-processor adapter defines these bits to select between DTE and DCE clocking options.
The DTE (inbound) transmit clock function is denoted by a logic 0.
In this case, the transmit clock for a particular port is supplied
by the co-processor adapter card.
The DCE (inbound) transmit clock function is denoted by a logic 1.
In this case, the transmit clock for a particular port is supplied
by an external device, such as a modem.
Power-up: UUUU UUUU
Reset command: UUUU UUUU
The SIMM configuration register is a co-processor adapter read-only register. It provides a binary-encoded decimal value that identifies the memory SIMM being used as to memory size and speed sort.
I/O Addresses
-------------
Co-Processor Adapter
SIMMCONFIG = 0802h
System Unit = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ SIMMCONFIG
| | | | | | | |
| | | | | | | +----- SC0
| | | | | | +-------- SC1
| | | | | +----------- SC2
| | | | +-------------- SC3
| | | +----------------- Reserved
| | +-------------------- Reserved
| +----------------------- Reserved
+-------------------------- Reserved
Bits 0-3
These bits provide the binary-encoded decimal value for the
SIMM that specifies the memory size and the speed sort.
The two values defined for the co-processor adapter are:
Power-up: UUUU 1001 or UUUU 1010
Reset command: UUUU SSSS
The Signetics SCN26562 Dual Universal Serial Communications Controller (DUSCC) chip is used by the co-processor adapter for data communications. Up to four of these chips are supported by one co-processor adapter. Two of the DUSCCs reside on the co-processor adapter, and up to two DUSCCs can reside on the optional interface board. This provides the co-processor adapter with up to eight individually programmable ports for serial communications functions.
After initial configuring of the DUSCCs by the Realtime Control Microcode, a major portion of the serial communications workload is relieved from the 80C186 processor and is performed by the DUSCCs. (Refer to the appropriate Signetics publication for a detailed description of the SCN26562 DUSCC.)
The DUSCCs provide many versatile features, such as:
The DUSCCs provide controller logic for each of the data communications ports on the co-processor adapter. The DUSCC interfaces with the following components on the co-processor adapter:
The co-processor adapter block diagram shown at the beginning of this chapter provides an overview of the interconnections.
Each of the DUSCCs uses a single +5 volt power supply.
The DUSCC pin functions are shown in Figure 9.
PORT A
+-------------------------+ ------
+ <-->| D7 TxDA |---> +Serial data
| <-->| D6 RxDA |<--- +
| <-->| D5 |
Data bus | <-->| D4 TRxCA |<--> +Port clocks
| <-->| D3 RTxCA |<--> +
| <-->| D2 |
| <-->| D1 -RTSAN/SYNOUTIAN|---> +Port controls
+ <-->| D0 -CTSAN |<--- |for modem, DMA,
| -DCDDAN/SYNIAN|<:--- +or other
+ --->| A6 |
| --->| A5 |
Address | --->| A4 | PORT B
bus | --->| A3 | ------
| --->| A2 TxDB |---> +Serial data
+ --->| A1 RxDB |<--- +
| |
+ --->| -WRN TRxCB |<--> +Port clocks
80C186 | --->| -RDN RTxCB |<--> +
Bus timing | --->| -RDYN |
control & | --->| -CEN -RTSBN/SYNOUTIBN|---> +Port controls
reset + --->| -RESETN -CTSBN |<--- |for modem, DMA,
| -DCDDBN/SYNIBN|<--- +or other
+ <---| -IRQN |
Interrupt + --->| -IACKN |
| |
+ --->| -RTxDAKAN/GPI1AN |
| --->| -RTxDAKBN/GPI1BN |
| --->| -TxDAKAN/GPI2AN |
DMA | <-->| -TxDAKBN/GPI2BN |
interface | <---| -RTxDRQAN/GPO1AN |
| <---| -RTxDRQBN/GPO1BN |
| <---| -TxDRQAN/GPO2AN |
| <---| -TxDRQBN/GPO2BN |
+ <-->| -EOPN |
| X2 X1/CLK|
+-------------------------+
^ ^ ^
| | |
+5V GND PCLK
All possible functions and features available with the DUSCC registers are not possible on the co-processor adapter. The known programming restrictions of the DUSCC chip for the co-processor adapter are described in this section. Failure to comply with these restrictions will lead to unpredictable results.
Bit 5 Bit 4 Bit 3 ----- ----- ----- 0 1 1 : Duplex, dual-address 1 1 1 : Polled or interrupt
These are the only two valid bit combinations for bits 5 through 3 of CMR2. Use 011 for DMA mode operation, or 111 for polled or interrupt mode operation.
A channel cannot be dynamically reconfigured. Observe the following rules during write operations:
Do Not Write To Condition --------------- ------------------------------ CMR1, CMR2, S1R, When the channel is in use S2R, or PCR (receiver or transmitter enabled) RPR or RTR When the receiver is enabled TPR or TTR When the transmitter is enabled CTCR, CTPRH, or When the counter/timer is enabled CTPRL
The Realtime Control Microcode, along with PROM Services and Realtime Interface Co-Processor Extended Services, is designed to manage the programming of the DUSCC. However, the user may want to program the DUSCC directly to obtain certain performance improvements.
The DUSCC has an operating frequency of
14.7456 MHz to support most serial communication line speeds to 0.01%
tolerance. The co-processor adapter supports DUSCC data rates
up to 2.048M bits-per-second, provided
a clock of this speed is supplied to the
DUSCC, typically from a high-speed modem.
The DUSCC, with no externally supplied
clock, can support synchronous rates up to 230.4KB bits-per-second
half-duplex, and 57.6KB bits-per-second duplex using the digital
phase-locked loop (DPLL).
Also, the DUSCC can support asynchronous data rates up to
115.2KB bits-per-second duplex.
Figure 10.
Figure 10. DUSCC Clocking Rates Supported by Co-Processor Adapter
+----------+----------------+------------------+--------+--------+ | Rate | TXCLK Source | RXCLK Source | Half | Full | | (KB/sec) | Sync Async | Sync Async | Duplex | Duplex | +----------+-------+--------+---------+--------+--------+--------+ | 0-2048 | E | - | E | - | Yes | Yes | | 230.4 | C | - | DX | - | Yes | Yes | | 115.2 | - | R | - | R | Yes | Yes | | 76.8 | - | R | - | R | Yes | Yes | | 57.6 | C | C | DC | C | Yes | Yes | | 38.4 | C, B | C, B | DC, DB | C, B | Yes | Yes | | 28.8 | C | C | DC | C | Yes | Yes | | 19.2 | C, B | C, B | DC, DB | C, B | Yes | Yes | | 14.4 | C | C | DC | C | Yes | Yes | | 9.6 | C, B | C, B | DC, DB | C, B | Yes | Yes | +----------+-------+--------+---------+--------+--------+--------+
Rates lower than those shown in the table are also possible using either the Counter/Timer or Bit Rate Generator. Refer to the Signetics SCN26562 Product Specification for details.
The base addresses of the DUSCCs are listed
in Figure 11..
Figure 11. DUSCC Base Addresses
+------------+-------------+--------------------------+ | Device | Address | Comments | | | (hex) | | +------------+-------------+--------------------------+ | DUSCC0 | 1800 | Supports ports 0 and 1 | | DUSCC1 | 1900 | Supports ports 2 and 3 | | DUSCC2 | 1A00 | Supports ports 4 and 5 | | DUSCC3 | 1B00 | Supports ports 6 and 7 | +------------+-------------+--------------------------+
Multiple registers are used for each DUSCC channel that is programmed by the co-processor adapter to configure the functional personality of the channels. Direct addressing is used for all the data and control registers associated with the DUSCC. The co-processor adapter issues a series of commands to initialize the desired mode of operation. The final action is to set the receiver or transmitter enable.
Some of the program selectable options for configuring the DUSCC functional personality are as follows:
The DUSCC registers can be separated into five groups:
+----------+--------+--------+--------+------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+------------------------------+ | CMR1 | 00 | 40 | R/W | Channel Mode Register 1 | | CMR2 | 02 | 42 | R/W | Channel Mode Register 2 | | S1R | 04 | 44 | R/W | SYN1/Secondary Address 1 Reg | | S2R | 06 | 46 | R/W | SYN2/Secondary Address 2 Reg | | PCR | 1C | 5C | R/W | Pin Configuration Register | +----------+--------+--------+--------+------------------------------+
+----------+--------+--------+--------+--------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+--------------------------------+ | TPR | 08 | 48 | R/W | Transmitter Parameter Register | | TTR | 0A | 4A | R/W | Transmitter Timing Register | | RPR | 0C | 4C | R/W | Receiver Parameter Register | | RTR | 0E | 4E | R/W | Receiver Timing Register | | OMR | 16 | 56 | R/W | Output & Misc. Register | | TXFIFO | 20 | 60 | W | Transmitter FIFO | | RXFIFO | 28 | 68 | R | Receiver FIFO | +----------+--------+--------+--------+--------------------------------+
+----------+--------+--------+--------+-------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+-------------------------------+ | CTPRH | 10 | 50 | R/W | Counter/Timer Preset Reg High | | CTPRL | 12 | 52 | R/W | Counter/Timer Preset Reg Low | | CTCR | 14 | 54 | R/W | Counter/Timer Control Reg | | CTH | 18 | 58 | R | Counter/Timer High | | CTL | 1A | 5A | R | Counter/Timer Low | +----------+--------+--------+--------+-------------------------------+
+----------+--------+--------+--------+------------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+------------------------------+ | RSR | 30 | 70 | R/W | Receiver Status Register | | TRSR | 32 | 72 | R/W | Trans/Rec Status Register | | ICTSR | 34 | 74 | R/W | Input & C/T Status Register | | GSR* | 36 | 36 | R/W | General Status Register | | IER | 38 | 78 | R/W | Interrupt Enable Register | | (IVR) | 3C | | R/W | Interrupt Vector Reg (unmod) | | (IVRM) | 7C | | R | Interrupt Vector Reg (mod) | | (ICR) | 3E | | R/W | Interrupt Control Register | +----------+--------+--------+--------+------------------------------+Note:
Registers with asterisks (*s) are shared between ports A and B. Registers in parentheses ( ) are not port specific.
+----------+--------+--------+--------+--------------------------+ | | Port A | Port B | | | | Register | Offset | Offset | Access | Function | +----------+--------+--------+--------+--------------------------+ | CCR | 1E | 5E | R/W | Channel Command Register | | MRR | 7E | | R/W | Master Reset Register | +----------+--------+--------+--------+--------------------------+
The communication lines that the DUSCC supports in the co-processor adapter implementation are as follows:
Four other communication signals are handled through the CIO. These are detailed in the "Counter/Timer and Parallel I/O Unit (CIO)".
The DMA/peripheral interface chip acts as the interrupt arbiter for all DUSCC0-3 and CIO0-1 interrupts. The DMA/peripheral interface chip contains six command ports that are used to re-enable interrupts within the chip for the 80C186 that may be pending from DUSCC0 or CIO0.
During the interrupt subroutine, the user must do a byte I/O write to the appropriate command port to re-enable interrupts from that particular DUSCC or CIO device. The data is don't care. The I/O write to the particular DMAEOI command port must be at least two instructions after the write to the appropriate DUSCC status register that clears the interrupt. Both writes must be before the 80C186 EOI is issued.
The addresses for the particular DMAEOI command ports are as follows:
Figure 17. DMAEOI Command Port Addresses
+---------------+------------+ | Particular | Address | | DMAEOI | (hex) | +---------------+------------+ | DUSCC0 EOI | 3220 | | DUSCC1 EOI | 3221 | | DUSCC2 EOI | 3222 | | DUSCC3 EOI | 3223 | | CIO0 EOI | 3224 | | CIO1 EOI | 3225 | +---------------+------------+
Diagnostics are provided for the DUSCC. For diagnostic testing, the DUSCC is run in an internal data wrap mode, at various baud rates and bit modes. The DUSCC test routine is called by the power-on self-test (POST) and is callable by the user.
The 8036 Counter/Timer and Parallel I/O Unit (CIO) provides peripheral I/O support for the co-processor adapter. The co-processor adapter contains two CIO chips. Features of each CIO are:
Two 8-bit ports on each CIO (32 total bits) are used for peripheral I/O control of data through the co-processor adapter's interface boards. These 32 bits provide eight serial ports with four more control lines than are provided by the DUSCC. The additional control lines are as follows:
Five timers are available for application tasks running on the co-processor adapter.
Additional features include firmware support for CIO diagnostic routines, and user interfaces for performing PROM Services.
Figure 18. shows the pin functions for the 8036 CIO.
Figure 18. CIO Pin Functions
+----------------+
+ <-->| AD7 PA7 |<--> +
| <-->| AD6 PA6 |<--> |
Address/ | <-->| AD5 PA5 |<--> |
data bus | <-->| AD4 PA4 |<--> | Port A
| <-->| AD3 PA3 |<--> |
| <-->| AD2 PA2 |<--> |
| <-->| AD1 PA1 |<--> |
+ <-->| AD0 PA0 |<--> +
Bus timing + --->| AS PC3 |<--> +
and reset + --->| DS PC2 |<--> | Port C
+ --->| R/W PC1 |<--> |
Control | --->| CS1 PC0 |<--> +
+ --->| CS0 PB7 |<--> +
+ <---| INT PB6 |<--> |
| --->| INTACK PB5 |<--> |
Interrupt | --->| IEI PB4 |<--> | Port B
+ <---| IEO PB3 |<--> |
| PB2 |<--> |
| PB1 |<--> |
| PB0 |<--> +
+----------------+
^ ^ ^
| | |
+5V GND PCLK
One port and one timer of CIO0 are used by the watchdog timer to provide interrupt notification of a runaway CPU. The remaining ports on the two CIOs either are used as modem controls for the serial ports or are available for general-purpose I/O with custom interface boards. The remaining five timers are allocated to the user for application-specific requirements. The following tables show the bit assignments for CIO0 and CIO1.
CIO0 Bit Assignments
+--------+----------+ +--------+----------+ | Port A | Signal | | Port B | Signal | | Bit | Name | | Bit | Name | +--------+----------+ +--------+----------+ | PA0 | DTR0 | | PB0 | DSR0 | | PA1 | DTR1 | | PB1 | DSR1 | | PA2 | DTR2 | | PB2 | DSR2 | | PA3 | DTR3 | | PB3 | DSR3 | | PA4 | DTR4 | | PB4 | DSR4 | | PA5 | DTR5 | | PB5 | DSR5 | | PA6 | DTR6 | | PB6 | DSR6 | | PA7 | DTR7 | | PB7 | DSR7 | +--------+----------+ +--------+----------+CIO1 Bit Assignments
+--------+----------+ +--------+----------+ | Port A | Signal | | Port B | Signal | | Bit | Name | | Bit | Name | +--------+----------+ +--------+----------+ | PA0 | RI0 | | PB0 | HRS0 | | PA1 | RI1 | | PB1 | HRS1 | | PA2 | RI2 | | PB2 | HRS2 | | PA3 | RI3 | | PB3 | HRS3 | | PA4 | RI4 | | PB4 | HRS4 | | PA5 | RI5 | | PB5 | HRS5 | | PA6 | RI6 | | PB6 | HRS6 | | PA7 | RI7 | | PB7 | HRS7 | +--------+----------+ +--------+----------+See "Watchdog Timer" for Port C pin assignments.
The CIO peripheral clock (PCLK) has an operating frequency of 3.6864 MHz.
The watchdog timer (timer 3) operates at a frequency of 763 Hz (T3CLK). It has a range from 1.31 milliseconds to 86 seconds, in increments of 1.31 milliseconds. See "Watchdog Timer".
Refer to the appropriate Zilog publication for a detailed description of the 8036 Counter/Timer and Parallel I/O Unit.
Programming the CIO is accomplished by loading the CIO control registers with the proper bits to implement the desired operation modes. CIO counters/timers are treated as separate devices from the CIO ports. This allows greater flexibility in assigning timer resources. The timers can be driven from PCLK, which is 3.6864 Mhz. Some of the 8036 CIO features are not utilized by the co-processor adapter. These include the handshaking mode and its various options (de-skew and so forth).
The base addresses of the CIOs are:
CIO0: 0180h CIO1: 0500h
The CIO operates in left-shift mode. When performing I/O operations to the CIO, subsequent I/O operations must be separated by at least two processor instructions. A good instruction to use is JMP $+2. This is required because the 80C186 can process I/O operations faster than the CIO can handle them. Bit definitions for each register are in the Zilog Technical Reference.
The addresses of individual registers are as shown in the following tables:
The main control registers are dedicated for co-processor adapter use only and should not be written to directly by applications. Support for application tasks is provided by PROM Services.
+-----------------+-----------------+----------------------------------------+ | Offset | Access | Function | +-----------------+-----------------+----------------------------------------+ | 0000h | R/W | Master interrupt control register | +-----------------+-----------------+----------------------------------------+ | 0002h | R/W | Master configuration control register. | | | | Bit 4 is dedicated to the watchdog | | | | timer and should not be programmed. | | | | Bit 3 (=0) allows ports A and B to | | | | operate independently and should not be| | | | changed. | +-----------------+-----------------+----------------------------------------+ | 0004h | R/W | Port A interrupt vector. | +-----------------+-----------------+----------------------------------------+ | 0006h | R/W | Port B interrupt vector. | +-----------------+-----------------+----------------------------------------+ | 0008h | R/W | Counter/timer interrupt vector. | +-----------------+-----------------+----------------------------------------+ | 000Ah | R/W | Port C data path polarity register. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 000Ch | R/W | Port C data direction register. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 000Eh | R/W | Port C special I/O control register. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+
+-----------------+-----------------+----------------------------------------+ | Offset | Access | Function | +-----------------+-----------------+----------------------------------------+ | 0010h | R/W | Port A command and status. Bits 2-3 | | | | do not apply in the bit port mode. | +-----------------+-----------------+----------------------------------------+ | 0012h | R/W | Port B command and status. Bits 2-3 | | | | do not apply in the bit port mode. | +-----------------+-----------------+----------------------------------------+ | 0014h | R/W | Counter/timer 1 command and status. | +-----------------+-----------------+----------------------------------------+ | 0016h | R/W | Counter/timer 2 command and status. | +-----------------+-----------------+----------------------------------------+ | 0018h | R/W | Counter/timer 3 command and status. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 001Ah | R/W | Port A data register. | +-----------------+-----------------+----------------------------------------+ | 001Ch | R/W | Port B data register. | +-----------------+-----------------+----------------------------------------+ | 001Eh | R/W | Port C data register. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+
+-----------------+-----------------+----------------------------------------+ | Offset | Access | Function | +-----------------+-----------------+----------------------------------------+ | 0020h | R | Counter/timer 1 current count MSB. | +-----------------+-----------------+----------------------------------------+ | 0022h | R | Counter/timer 1 current count LSB. | +-----------------+-----------------+----------------------------------------+ | 0024h | R | Counter/timer 2 current count MSB. | +-----------------+-----------------+----------------------------------------+ | 0026h | R | Counter/timer 2 current count LSB. | +-----------------+-----------------+----------------------------------------+ | 0028h | R | Counter/timer 3 current count MSB. | +-----------------+-----------------+----------------------------------------+ | 002Ah | R | Counter/timer 3 current count LSB. | +-----------------+-----------------+----------------------------------------+ | 002Ch | R/W | Counter/timer 1 time constant MSB. | +-----------------+-----------------+----------------------------------------+ | 002Eh | R/W | Counter/timer 1 time constant LSB. | +-----------------+-----------------+----------------------------------------+ | 0030h | R/W | Counter/timer 2 time constant MSB. | +-----------------+-----------------+----------------------------------------+ | 0032h | R/W | Counter/timer 2 time constant MSB. | +-----------------+-----------------+----------------------------------------+ | 0034h | R/W | Counter/timer 3 time constant MSB. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 0036h | R/W | Counter/timer 3 time constant LSB. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 0038h | R/W | Counter/timer 1 mode specification. | +-----------------+-----------------+----------------------------------------+ | 003Ah | R/W | Counter/timer 2 mode specification. | +-----------------+-----------------+----------------------------------------+ | 003Ch | R/W | Counter/timer 3 mode specification. | | | | (Reserved for co-processor | | | | adapter use only.) | +-----------------+-----------------+----------------------------------------+ | 003Eh | R/W | Current vector. | +-----------------+-----------------+----------------------------------------+ | MSB = Most significant byte | | LSB = Least significant byte | +----------------------------------------------------------------------------+
+-----------------+-----------------+-----------------------------------------+ | Offset | Access | Function | +-----------------+-----------------+-----------------------------------------+ | 00040h | R/W | Port A mode specification. Bits 3-7 | | | | must be 0s to keep the port specified | | | | as in bit port mode. The de-skew timer | | | | function is not support. Therefore | | | | bit 0 is for latch-on pattern match. | +-----------------+-----------------+-----------------------------------------+ | 00042h | R/W | Port A handshake specification. | | | | Register ia always 0, | | | | since handshaking is not utilized. | +-----------------+-----------------+-----------------------------------------+ | 00044h | R/W | Port A data path polarity. | +-----------------+-----------------+-----------------------------------------+ | 00046h | R/W | Port A data direction. | +-----------------+-----------------+-----------------------------------------+ | 00048h | R/W | Port A special I/O control. | +-----------------+-----------------+-----------------------------------------+ | 0004Ah | R/W | Port A pattern polarity. | +-----------------+-----------------+-----------------------------------------+ | 0004Ch | R/W | Port A pattern transition. | +-----------------+-----------------+-----------------------------------------+ | 0004Eh | R/W | Port A pattern mask (which bits to test)| +-----------------+-----------------+-----------------------------------------+
+-----------------+-----------------+----------------------------------------+ | Offset | Access | Function | +-----------------+-----------------+----------------------------------------+ | 00050h | R/W | Port B mode specification. | +-----------------+-----------------+----------------------------------------+ | 00052h | R/W | Port B handshake specification. | +-----------------+-----------------+----------------------------------------+ | 00054h | R/W | Port B data path polarity. | +-----------------+-----------------+----------------------------------------+ | 00056h | R/W | Port B data direction. | +-----------------+-----------------+----------------------------------------+ | 00058h | R/W | Port B special I/O control. | +-----------------+-----------------+----------------------------------------+ | 0005Ah | R/W | Port B pattern polarity. | +-----------------+-----------------+----------------------------------------+ | 0005Ch | R/W | Port B pattern transition. | +-----------------+-----------------+----------------------------------------+ | 0005Eh | R/W | Port B pattern mask. | +-----------------+-----------------+----------------------------------------+
As a preventive device, a watchdog timer has been incorporated on the co-processor adapter card. This timer, once activated, must continually be strobed by software so that it will not time out. If the 80C186 processor ever has a fatal error, this timer will reach its terminal count. The terminal count will:
The range for the watchdog timer is from 1.31 milliseconds to 86 seconds, with a step size of 1.31 milliseconds.
The watchdog timer is timer 3 in CIO0. The following table shows that if the watchdog timer is never initialized, the LED will stay on. The user can control the LED directly by clearing PC2, or allow it to be controlled by the watchdog timer.
+--------+-----+--------+--------------------------------+ | CIO0 | | | | | Port C | Pin | Signal | Description | +--------+-----+--------+--------------------------------+ | PC0 | 21 | WDOG | Timer 3 output, Watchdog Timer | | PC1 | 22 | T3CLK | Timer 3 clock input, 763 Hz | | PC2 | 23 | WD CNTL| Watchdog LED control | | PC3 | 24 | RSVD | Reserved | +--------+-----+--------+--------------------------------+ +-----------+--------+ | CIO0 | | | Port C | LED | +-----+-----+ Status | | PC2 | PC0 | | +-----+-----+--------+ | 0 | 0 | On | | 0 | 1 | On | | 1 | 0 | Off | | 1 | 1 | On | +-----+-----+--------+
The RAM controller and bus master interface chip (RCBMIC) is an IBM CMOS II gate array, containing 20000 gates. This chip provides a convenient and flexible way of passing data and control bytes between the 80C186 bus and the system unit bus. The VLSI gate array's basic purpose is to provide a high-performance interface between the co-processor adapter and the system unit. All data communications between the system unit and the co-processor adapter are done through this interface.
The RAM controller and bus master interface chip provides the following functions to the co-processor adapter:
The subsections that follow summarize the internal registers contained within the RAM controller and bus master interface chip. Detailed register descriptions and bit definitions are located in Appendix A. "RAM Controller and Bus Master Interface Registers".
+------------------------+----------+----------+----------+-----------+ | | POS | Sys Unit | Co-Proc. | Power-Up | | | Address | Address | Adapter | Value | | Register Name | (hex) | (hex) | Address | (Note 3) | | | (Note 5) | (Note 1) | (hex) | | +------------------------+----------+----------+----------+-----------+ | BMCH (Note 2) | - | - | 20 - 2E | ---- ---- | | BMCH1RESET (Note 2) | - | - | A0 | ---- ---- | | CRDIDREG (Upper 8 bits)| 00 | - | 88 | 0000 0000 | | CRDIDREG (Lower 8 bits)| 01 | - | 88 | 0000 0000 | | CPUPG | - | 05 | 14 or 5E | UUUU UUUU | | DMAPG | - | (20)-(3C)| 40 - 5C | UUUU UUUU | | GAID | - | (0F) | 18 | 1000 0001 | | INITREG0 (Note 4) | 02 | (12) | 04 | 0000 0000 | | INITREG1 | - | (10) | 06 | 0000 0000 | | INITREG2 (Note 4) | - | (08) | - | 0000 0000 | | INITREG3 | 05 | (13) | 1A | 0000 0000 | | INTIDREG (Upper 8 bits)| - | - | 92 | 0000 0000 | | INTIDREG (Lower 8 bits)| - | - | 92 | 0000 0000 | | INTOSTAT | - | - | 90 | 0000 0000 | | IOCHCK | - | - | 94 | 0000 0000 | | LOCREG0 | 03 | 00 | 00 | UUUU UUUU | | LOCREG1 | 04 | 01 | 02 | 000U UUUU | | NMIMASK (Upper 8 bits) | - | - | 08 | 0000 1111 | | NMIMASK (Lower 8 bits) | - | - | 08 | 0011 1111 | | NMISTAT (Upper 8 bits) | - | - | 0A | 0000 0000 | | NMISTAT (Lower 8 bits) | - | - | 0A | 0000 0000 | | PCCSTAT | - | (14) | 8A | 0UUU UUUU | | PCPAR0 | - | (0A) | 96 | UUUU UUUU | | PCPAR1 | - | (0B) | 98 | UUUU UUUU | | PCPAR2 | 05 | (11) | 9A | 011U UUUU | | PESTAT (Upper 8 bits) | - | - | 8C | 000U UUUU | | PESTAT (Lower 8 bits) | - | - | 8C | UUUU UUUU | | PROCSYNC | - | 07 | 8E | 0000 0000 | | RICPAR0 | - | - | 0C | 000U UUUU | | RICPAR1 | - | - | 0E | UUUU UUUU | | RICPAR2 | - | - | 10 | 000U UUUU | | TREG | - | 04 | 12 or 16 | 1111 1111 | | TRAN0-63 | - | - | C000-C07E| ---- ---- | | TTPROTON (Note 2) | - | - | 9C | N/A | | TTPROTOFF (Note 2) | - | - | 9E | N/A | +------------------------+----------+----------+----------+-----------+
Notes:
1. Values given in parentheses are pointer register values.
All other values are offsets and should be added
to the base address value programmed in INITREG0.
2. Default power-up values are not applicable.
3. 0=logic level 0; 1=logic level 1.
S=same or no change; U=undefined.
4. INITREG2 is only three bits of INITREG0 and is system unit
read-only, while INITREG0 is all eight bits and is
read/write by both CPUs.
5. POS address offsets are further encoded with a valid
card enable (CARDEN).
Each co-processor adapter card is assigned a system memory address range at Programmable Option Select (POS) time. This range is selected as either 8KB, 16KB, 32KB, 64KB, 128KB, 512KB, 1MB, or 2MB bytes in length, and can be mapped anywhere within each of four 16MB regions as follows:
The 8KB, 16KB, 32KB, 64KB, 128KB, 512KB, 1MB, or 2MB of system memory described previously is actually part of the 80C186 addressable memory space. (hence the term dual-ported memory. Both processors, the system unit and the 80C186, have access to the same memory, with arbitration transparent to either processor. In general, this dual-ported memory is how the two processors communicate. They coordinate their activities using interrupts and control blocks set up in shared memory. Typically, small data transfers from system-to-card or vice versa are shared memory transfers, and large data transfers are bus-master driven.
The default master of the system has the ability to page through all of the co-processor adapter's memory and view all data present there. This paging is done through the processor page register. Once the window size is set at POS time, the default master can change the value of the processor page register and look throughout memory. For example, if the co-processor adapter has 1MB of on-card memory and the window size is 8KB, a value of 04h programmed into the processor page register allows the default master to view the fifth 8KB page of 128 possible 8KB pages of co-processor adapter storage. A value of 00h in the processor page register allows viewing of the first 8KB page.
This concept has been carried forward to allow any master on the system unit bus to address the co-processor adapter as a slave through its own unique DMA page register. This register is selected automatically by the hardware, based on the arbitration level present on the bus during any bus cycle. There are now 16 individual page registers on the co-processor adapter, one for all possible bus arbitration levels. As long as any master knows the system address range of a co-processor adapter card, it can have a unique data port into the co-processor adapter memory. Also, these page registers are themselves pointed to by a decode of the bus arbitration level. Therefore, they are all at the same I/O address location as seen from any bus master. This allows any master capable of performing I/O-type bus cycles to change its DMA page register and view all the co-processor adapter's slave memory, just as the default master does.
Since the co-processor adapter bus master has all of these requirements, a peer-to-peer co-processor adapter relationship is possible.
As a memory slave, the co-processor adapter's performance is looked at in terms of the number of wait states that are inserted into any particular system unit bus master cycle (default master or any other).
Since the memory controller arbitrates memory requests between four different requesting sources (see Figure 23.), the number of wait states inserted in any particular cycle can vary depending on the degree of contention.
In the worst case, if all other requests are active, a cycle could take up to 1.2 micro seconds (&usec.) to complete, essentially 10 wait states. In the best case, if no other requests are active, a cycle will take 500 nanoseconds (ns), or 3 wait states. On average, cycle times should be 600 to 700 ns, or 4 to 5 wait states.
The co-processor adapter supports two different and independent data transfer interfaces to the Micro Channel. One is a first-party DMA/Bus Master (BM) interface, and the other is a memory-mapped I/O slave (MM) interface. Both interfaces provide a 16-bit data path and 32 bits of addressability.
The BM interface supports one full-function DMA channel. This channel can be used for both card-to-system and card-to-card transfers.
The channel's registers are organized as an 8-word channel descriptor block (CDB), loadable through 80C186 I/O instructions. Once initialized, the channel can be started with an I/O write to its channel control register (CCR).
To improve performance on the Micro Channel, transfers to and from the Micro Channel are buffered on the card in a 32 x 16 buffer. This allows 200-ns cycles on the Micro Channel when accessing a 0 wait-state memory. Using 200-ns cycles, all 32 words in the buffer are transferred to and from the buffer during a single 6.4 &usec. burst cycle.
The 32 x 16 buffer also improves transfers to and from another co-processor adapter card. Cycle time on the Micro Channel is variable due to the shared memory architecture of the co-processor adapter slave memory. Typical cycle times average 700-ns-per-word transfer. As many cycles as possible, up to 32, are performed within the prescribed 7.8 &usec. timeout limit from active PREEMPT on the bus.
The channel has an 8-word channel descriptor block (CDB).
The CDB is loadable in the 80C186 I/O address
space through 16-bit I/O instructions.
The CDB register I/O map is shown in Figure 19..
Figure 19. CDB Register I/O Map
+--------------------------------+---------+ | Channnel Descriptor | Address | | Block (CDB) Register | | +--------------------------------+---------+ | List Address Pointer 0-15 | 2Eh | | | | | List Address Pointer 16-20 | 2Ch | | | | | Channel Control Register | 2Ah | | | | | System Address Register 0-15 | 28h | | | | | System Address Register 16-31 | 26h | | | | | Card Address Register 0-15 | 24h | | | | | Card Address Register 16-20 | 22h | | | | | Transfer Count Register | 20h | +--------------------------------+---------+
The registers for each channel are detailed in the sections that follow.
The channel control register (CCR) is the control and command area for a channel. It is loaded initially by an 80C186 I/O write, and subsequently either is reloaded by more I/O writes, or, if list chaining is enabled, loaded by the hardware during memory list accesses. In this way, dynamic control of the channel is possible.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|XX|XX|XX|XX|XX|XX|XX|XX|SC|MI|CA|SA|LE|TC|DR|SS|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Bit 0, Start/Stop
When this bit is set to 1, it indicates
the channel is in the process of performing transfers.
When this bit is reset to 0, it
indicates the channel is idle.
This bit is set by the programmer to initiate a transfer.
Hardware will reset the bit to
indicate the transfer has completed.
Writing a 0 to this bit
terminates the present transfer after the cycle in process
has completed.
No internal counters are reset, so that a
subsequent write of 1 will continue the transfer where it left off.
In addition, reading this bit does not return a 0, unless the cycle has completed and the channel is stopped. Therefore, the bit provides status for the channel, as well as controlling its function.
When this bit is set to 1, no other bit in the CCR can be updated by a direct I/O write from the 80C186. This feature allows the start/stop bit to be reset without corrupting the transfer currently executing.
This bit is not updated during list chaining, but all other bits in the CCR are updated. This feature allows the register to be loaded with new values during list chaining without resetting the start/stop bit.
Bit 1, Direction
This bit signifies the direction of data
transfer on the Micro Channel.
When this bit is set to 1, it indicates data is to be read
from the Micro Channel to the card.
When this bit is reset to 0, it indicates
data is to be written from the card to the Micro Channel.
This bit should not be written while the SS bit is active.
Bit 2, Terminal Count Interrupt to 80C186 Enable
If this bit is set to 1,
an interrupt is presented to the 80C186 when the
Channel Counter Register (CCR) transitions from 0001h to 0000h.
If this bit is reset to 0, no interrupt occurs.
Bit 3, List Chaining Enable
When this bit is set to 1,
list chaining is enabled; when it is reset to
0, list chaining is disabled. For more information, see
"List Chaining".
Bit 4, System Address Increment/Decrement
When this bit is set to 1, it
increments the value in the system address register after
each transfer. When this bit is reset to 0, it decrements the
value in the system address register after each transfer.
Bit 5, Card Address Increment/Decrement
When this bit is set to 1, it
increments the value in the card address register after each
transfer. When this bit is reset to 0, it decrements the
value in the card address register after each transfer.
Bit 6, Memory I/O Transfer
When this bit is set to 1, it indicates the channel is to
perform a memory-type Micro Channel bus cycle.
When this bit is reset to 0,
it indicates the channel is to perform
an I/O type Micro Channel bus cycle.
Bit 7, Stop Channel after List Chaining
This bit is active only when the list chaining bit (LE) is set.
If this bit is set to 1 and the LE bit also is set to 1,
the channel will stop after the current list chaining operation;
that is, the list chaining operation in which the bit is set.
If this bit is reset to 0,
the channel will continue to do transfers after the
current list chaining operation.
The channel always stops after the current transfer, when the
list chaining enable (LE) is not set.
This register contains the 16-bit value that signifies the number of bytes that are transferred before a terminal count is reached. This register is decremented by either one or two on the first transfer in order to word-address-align all subsequent transfers. The subsequent transfers decrement the value by two, until the last transfer, which decrements the register by one or two, depending on whether an even or odd transfer count was programmed. In this way, the most efficient transfer of data is achieved.
A value of 0000h programmed into this register causes 65536 bytes to be transferred before terminal count. The terminal count interrupt, if enabled, occurs when the count has gone from 0001h to 0000h and the RAM buffer has emptied.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|C15|C14|C13|C12|C11|C10| C9| C8| C7| C6| C5| C4| C3| C2| C1| C0|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The system address register (SAR) is a 32-bit register that contains the physical Micro Channel address of the next data word to be transferred. The register can be loaded with either an odd or even address.
The address is loaded initially through two I/O writes from the 80C186. Subsequent loading of the address is either by I/O writes or by hardware accesses to the list table in memory, if list chaining is specified.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|S15|S14|S13|S12|S11|S10| S9| S8| S7| S6| S5| S4| S3| S2| S1| S0|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|S31|S30|S29|S28|S27|S26|S25|S24|S23|S22|S21|S20|S19|S18|S17|S16|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The card address register (CAR) is a 21-bit register that contains the physical card memory address of the next data word to be transferred. If an odd byte count is specified in the TCR, the last transfer to the RAM buffer will be a byte. This value is loaded initially through two I/O writes from the 80C186. Subsequent loading of this value is either by I/O writes or by hardware accesses to the list table in memory, if list chaining is specified.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|C15|C14|C13|C12|C11|C10| C9| C8| C7| C6| C5| C4| C3| C2| C1| C0|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| X | X | X | X | X | X | X | X | X | X | X |C20|C19|C18|C17|C16|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
The list address pointer (LAP) is a 21-bit register that contains an address of an 80C186 memory location where a list of CDB information exists. This register must contain a physical address, which is on an even address boundary (that is, L0=0). The register must initially be loaded with two I/O write instructions. After initialization, the register can optionally be loaded again with an I/O write instruction or, if list chaining is enabled, it can automatically be reloaded by the hardware from the list table entry in memory. The LAP entry in memory must contain an even-aligned address (that is, L0=0). It is always incremented by two, following the movement of one of the list table entries into the CDB. This value will then be present if the LAP is read. More information on list chaining can be found in "List Chaining".
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|L15|L14|L13|L12|L11|L10|LC9| L8| L7| L6| L5| L4| L3| L2| L1| L0|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| X| X| X| X| X| X| X| X| X| X| X|L20|L19|L18|L17|L16|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
This 8-bit, read/write register is used to reset the internal bus master registers and control logic to a known state. During normal operation, it is not necessary to use this register. The address of the register is 00A0h.
MSB LSB
Bit 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| X | X | X | X | X | X | X |DIS|
+---+---+---+---+---+---+---+---+
Bit 0, DIS
When this bit equals 1, it resets the CH1 internal registers and
control logic and holds the channel in this reset state.
When this bit equals 0, it releases
the channel from the reset state for further operation.
Bits 1-7, Reserved
These bits are always read as 0s.
There are two types of list chaining: buffer and link.
The co-processor adapter BM DMA controller supports a feature known as buffer list chaining (BLC) or scatter/gather DMA. This feature allows the programmer to create, in memory, lists of different data buffer areas and buffer counts. The contents of the lists can be reloaded automatically to the CDB after a terminal count for the present data buffer is reached. The programmer has the option of either interrupting or not interrupting the 80C186 when this terminal count is reached. Also, certain control information in the CCR can be changed on-the-fly, which allows for dynamic changing of DMA parameters.
A 21-bit address pointer to the list in memory is maintained within the CDB. If list chaining is enabled at the time of terminal count, the hardware fetches six 16-bit words, starting at this memory address, and reloads the CDB at hardware speeds.
At the end of this operation,
the list address pointer in the CDB is
pointing to an address equal to the previous address, +Ch (12, decimal).
This address contains the next CDB list to be loaded when the newly
loaded terminal count is reached.
This provides a mechanism
to offload the 80C186 from processing DMA terminal count interrupts.
In theory, this list of buffers could occupy any amount of free
contiguous memory.
Buffer list chaining is shown in Figure 20..
Figure 20. CDB Buffer List Chaining
Channel Descriptor Block (CDB) Memory
0 15
+--------------------------+
List Address Pointer (LAP) ----->| Transfer Count |
(Always even-address aligned) +--------------------------+
| Card Address | LAP + 2
+--------------------------+
| Card Address 0-15 | LAP + 4
+--------------------------+
| System Address 16-31 | LAP + 6
+--------------------------+
| System Address 0-15 | LAP + 8
+--------------------------+
| Channel Control Register | LAP + Ah
+--------------------------+
| Start of Next List | LAP + Ch
+--------------------------+
In addition to buffer list chaining, the hardware provides a mechanism to allow these lists of buffer information to occupy non-contiguous areas of memory and be dynamically linked through information present in the list. This is known as linked list chaining (LLC), which is a special case of BLC.
When terminal count is reached and list chaining is enabled,
the first memory fetch (equals 0000h)
causes the hardware to fetch eight
additional 16-bit words, instead of
five additional words as in BLC.
This technique is detailed in Figure 21..
Figure 21. CDB Link List Chaining (LLC)
Channel Descriptor Block (CDB) Memory
0 15
+--------------------------+
List Address Pointer (LAP) ----->| 0000h (List Count) |
(Always even-address aligned) +--------------------------+
| Transfer Count | LAP + 2
+--------------------------+
| Card Address 16-20 | LAP + 4
+--------------------------+
| Card Address 16-31 | LAP + 6
+--------------------------+
| System Address 16-31 | LAP + 8
+--------------------------+
| System Address 0-15 | LAP + Ah
+--------------------------+
| Channel Control Register | LAP + Ch
+--------------------------+
| List Address 16-20 | LAP + Eh
+--------------------------+
| List Address 0-15 | LAP + 10h
+--------------------------+
At the end of this operation, the CDB contains a new pointer to a new list located anywhere else in memory.
The BM DMA channel can interrupt the 80C186 on a terminal count condition. Also, any system unit bus master can interrupt the 80C186. Both of these sources of interrupt are presented to the 80C186 on the INT0 line. The two sources are:
Since both sources share a single physical interrupt line to the 80C186, the interrupt routine must first read primary status register INT0STAT. This 2-bit register indicates the interrupting source. If the system unit bus master interrupt bit is set, a second read of the INTIDREG register is done to identify which bus master presented the interrupt.
The BM channel buffers data as it moves
between card memory and Micro Channel memory (non-system or system
memory). This method is shown in Figure 22..
Figure 22. Bus Master Operation
Co-Processor
Micro Channel Adapter Card A
+--------+ +--------+ +--------+
| | | 32 X 16| | |
| System | | High- | | Card A |
| Memory |<-------->| Speed |<-------->| Memory |
| | | Buffer | | |
| | | | | |
+--------+ +--------+ +--------+
The channel manages the movement of data from card to Micro Channel through its buffer. For data reads from the Micro Channel, the channel first arbitrates for the system bus and when granted, fills its buffer and then releases the bus. The channel then flushes its buffer to card memory. The channel continues this arbitrate/release/flush sequence until terminal count is reached. For data writes to the Micro Channel, this operation is reversed: fill/arbitrate/release.
To fill/flush its buffer to card memory, the channel must
arbitrate with other requesting memory arbiters.
There are four requesting arbiters
for co-processor adapter memory as illustrated in Figure 23..
Figure 23. Co-Processor Adapter Memory Arbiters
+---------+ +---------+
Bus Master ------>| | | |
Channel | | | |
| Arbiter +--------->| Arbiter +----> Memory
Refresh -------->| Logic | | Logic | Request
| | | |
System Unit ----->| | +---->| |
+---------+ | +---------+
|
80C186 --------------------------+
Note that there are two stages to the arbiter logic. This allows the 80C186 to gain control of memory at least every other cycle, guaranteeing an absolute maximum of 2 wait states per cycle, or 480 ns.
However, any other requesting arbiter can take as many as 6 memory cycle times to perform its cycle. Each memory cycle averages 200 ns. This means any of these requests could take an absolute maximum of 1.2 &usec. to service.
A more realistic maximum would take into account the relative infrequency of refresh requests, and lead to an average maximum cycle time of about 800 ns to service a bus master channel or system unit request.
The average typical cycle time to service a bus master channel or system unit request should be about 600 ns.
The following is a list of exceptions that stop the bus master channel.
The DMA/peripheral interface chip (DMAPIC) is an IBM CMOS II gate array, containing 10000 gates. This chip provides the following functions to the co-processor adapter:
The subsections that follow summarize the internal registers contained within the DMA/peripheral interface chip. Detailed register descriptions and bit definitions are located in Appendix B. "DMA/Peripheral Interface Registers/Commands".
+------------------------+----------+-------------+-----------+ | | Sys Unit | Co-Proc. | Power-Up | | | Address | Adapter | Value | | Register/Command | (hex) | Address | (Note 1) | | | | (hex) | | +------------------------+----------+-------------+-----------+ | DMAASSIGN | - | 8212 | N/A | | DMADISABLE | - | 8214 | N/A | | DMASTAT | - | 8200 - 820F | N/A | | DMASSO -15 | - | 8000 - 81FE | (Note 2) | | DMAVECTOR | - | 8210 | N/A | | DMAEOI | - | 3220 - 3225 | N/A | | DB ROS CS | - | E000 - EFFF | N/A | | DB I/O CS | - | F000 - FFFF | N/A | +------------------------+----------+-------------+-----------+Notes:
The functions of the DMA portion of the DMA/peripheral interface chip include the following:
Each of the 16 DMA channels are of equal function. One channel is dedicated to each of the transmit and receive channels for up to eight serial ports. The service priority is round robin and, within the round robin, the priority is fixed (from highest to lowest) as follows:
Prior to use, each channel must be initialized via I/O write commands from the 80C186 to the channel descriptor table (CDT). Also, if list chaining is enabled, a chain table must be set up in memory before the channel is enabled. (This is described in detail in "List Chaining".) Once enabled, a channel will service DMA requests from the DUSCC chip until one of a number of programmable conditions is reached. If the user has programmed the DMA channel to stop on one of these conditions, the channel can only be re-enabled through an I/O write to the channel control word (CCW). Each of these conditions also has the ability to interrupt the 80C186 through an interrupt vector and interrupt status mechanism. Also, the channel has the ability to interrupt without disabling the channel. All of the options are programmable in the CCW and are described in "Channel Control Word (CCW)".
Once a DMA request has been issued by the DUSCC, and the bus interface logic (BIL) has gained control of the local (80C186) bus, the DMA controller performs two separate bus cycles to move the data either from or to memory and the I/O port. After completion, the BIL gives control of the bus back to the 80C186 for further program execution, as long as no further DMA requests are pending. If another request is pending, this is serviced contiguously with the previous request before control is given back to the 80C186.
Figure 24.
This table is duplicated for each of the 16 DMA channels.
The table exists in the I/O space of the 80C186 and
is accessible through 16-bit I/O-type instructions.
The specific I/O addresses are listed in "I/O Address Map".
Figure 24. Channel Descriptor Table (CDT)
Address
+-----------------------------+
| List Address Pointer 0-15 | 8XXEh
| |
| List Address Pointer 16-20 | 8XXCh
| |
| Target Address 16-20 | 8XXAh
| |
| Transfer Count | 8XX8h
| |
| I/O Address 0-15 | 8XX6h
| |
| Character Match Bytes | 8XX4h
| |
| Target Address 0-15 | 8XX2h
| |
| Channel Control Word | 8XX0h
+-----------------------------+
The bit descriptions for each of the registers in the CDT are described in the following paragraphs. All registers power-up in an undefined state, except for the enable/disable bit (bit 0) of the CCW which is reset (disabled state) after power-up or when a reset command is issued to the card.
This register controls the operation of the DMA channel. All bits are written over during list chaining reload cycles, except the enable/disable bit (bit 0). Therefore, care must be taken when loading memory with this word, if list chaining is enabled.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | |Character| Stop | | List | Define | | |Match | Channel | Interrupt | Chain | Channel | | |Options | Options | Options | Options | Options | +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ |RSVD|CM2 |CM1 |STOP|STOP|STOP|STOP|INT |INT |INT |LC |LC |LC |BYTE|REC/|EN/ | | | | |EOM |A CM| CM |TC=0|EOM |CM |TC=0|EOM |CM |TC=0|WORD|TRAN|DIS | +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
Bit 0, +Enable/-Disable Channel
When this bit is set to 1,
the channel is enabled to service DMA requests;
when it is reset to 0,
the channel is unable to service DMA requests.
This bit can be used to disable the channel at any time.
Re-enabling the channel
causes the DMA operation to start where it left off.
Also, any
programming option that disables the channel is reflected in this bit.
This bit is not updated with its corresponding bit in memory during
list chaining reads from memory.
Bit 1, -Receive/+Transmit Indicator
When this bit is set to 1,
the channel services transmit DMA requests;
when it is reset to 0,
the channel services receive DMA requests.
For the co-processor adapter implementation, the channels should be programmed as follows:
Bit 2, -Byte/+Word Transfer Indicator
When this bit is set to 1,
it indicates word-wide transfers are being used;
when it is reset to 0,
it indicates byte-wide transfers are being used.
This bit should be programmed to a 0, as all transfers to and from the
DUSCC are byte-wide.
The hardware does word-wide transfers on
list reload cycles to the CDT, regardless of the state of
this bit.
Bit 3, List Chaining Enable for Terminal Count
When this bit is set to 1,
list chaining is enabled for terminal count;
when it is reset to 0,
list chaining is disabled for terminal count.
Bit 4, List Chaining Enable for Character Match
When this bit is set to 1,
list chaining is enabled for character match;
when it is reset to 0,
list chaining is disabled for character match.
The matching condition is that which is programmed in bits 13 and 14
of the CCW.
Bit 5, List Chaining Enable for End-of-Message
This is a dual-function bit whose usage is defined one way if the channel
is a receive channel, and another way if it is a transmit channel.
For a receive channel, the bit is defined as follows:
For a transmit channel, the bit is defined as follows:
Bit 6, Interrupt on Transfer Count = 0 Enable
When this bit is set to 1,
an interrupt occurs as the transfer count
goes from 0001h to 0000h; when it is reset to 0,
this type of interrupt is disabled.
Bit 7, Interrupt on Character Match Enable
When this bit is set to 1,
an interrupt occurs if the programmed
condition of bits 13 and 14 also occurs; when it is reset to 0,
this is type of interrupt is disabled.
In either case, status is retained in the DMASTAT register.
Bit 8, Interrupt on End-of-Message Condition
This bit is valid only if the channel is programmed as a receive channel.
When this bit is set to 1, an interrupt occurs if the DMA/peripheral interface chip
detects the DUSCC EOPN (see DUSCC manual) with the transfer of a DMAed
character. Status is retained in the DMASTAT only if this bit
is set to a 1. When this bit is reset to 0,
this interrupt is disabled.
(It should be programmed this way if the
channel is a transmit channel.)
Bit 9, Stop DMA Channel When Transfer Count = 0000h
When set to 1,
this bit causes the channel to stop servicing requests when the transfer
count reaches 0000h. When it is reset to 0, transfers continue if this
count-condition occurs.
Bit 10, Stop DMA Channel when the Condition Indicated by Bits
13 and 14 Occurs
When this bit is set to 1,
it causes the DMA channel to stop servicing
requests when a match of type indicated by bits 8 and 9 occurs.
When this bit is reset to 0, the
DMA continues servicing requests after the matching condition occurs.
Bit 11, Stop Associated Transmit Channel when Character Match
Occurs Enable
When this bit is set to 1, the associated transmit channel
is stopped when a character match occurs.
If a transfer is pending, it will be completed.
When this bit is reset to 0,
the associated transmit channel is not stopped on a character match.
Bit 12, Stop DMA Channel when End-of-Message
Condition Is Detected
This bit is only defined if the channel is programmed for receive DMA.
When set to 1,
this bit causes the channel to stop servicing receive requests
if the End-of-Message condition is detected. When it is reset to 0,
the channel
continues to service receive requests if the condition occurs.
This bit should be reset to 0 if the channel is programmed for transmit.
Bits 13 and 14, Character Match Logic
These bits are encoded as follows to indicate the function of the
character match logic:
Bit 15, Reserved
This bit should always be programmed to 0 to
allow for compatibility with future enhancements.
Note:
There are many possible programming options for the CCW. When any of the STOP options are selected and list chaining is enabled, the list is read from memory and the CDT is updated before the channel is stopped. The STOP options prevent the external DMA request from the DUSCC from starting a DMA operation.
This register contains the lower 16 address bits of the next DMA cycle to be executed. It must contain a physical address, and be initially loaded through an I/O write instruction. After initialization, the register can optionally be loaded again through I/O write instructions or, if list chaining is enabled, it is reloaded automatically by the hardware from the list table entry in memory. The TAR register is always incremented following a DMA cycle, and the new address is entered in the CDT.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
|TA15|TA14|TA13|TA12|TA11|TA10|TA9|TA8|TA7|TA6|TA5|TA4|TA3|TA2|TA1|TA0|
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
This register contains the upper five bits of the next DMA cycle to be executed. It must contain a physical address, and be initially loaded through an I/O write instruction. After initialization, this register optionally can be loaded again through I/O write instructions or, if list chaining is enabled, it is reloaded automatically by the hardware from the list table entry in memory. The TARE register is always incremented following a DMA cycle, and this new address is entered in the CDT.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+
| XX| XX| XX| XX| XX| XX| XX| XX| XX| XX| XX|TA20|TA19|TA18|TA17|TA16|
+---+---+---+---+---+---+---+---+---+---+---+----+----+----+----+----+
This register contains the 16-bit I/O address of the transmit or receive buffer of the DUSCC, depending on whether the RT bit of the CCW is programmed for receive or transmit. This value is loaded by an I/O write instruction at initialization time. It is neither incremented nor decremented and, generally, never has to be accessed again.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
|IA15|IA14|IA13|IA12|IA11|IA10|IA9|IA8|IA7|IA6|IA5|IA4|IA3|IA2|IA1|IA0|
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
This register contains the lower 16 address bits of a pointer into memory where a table exists to update a channel's descriptor block. This table is accessed when any of the following conditions exist:
The register must contain a physical address that is on an even address boundary (that is, LA0=0), and be loaded initially through an I/O write instruction. After initialization, it optionally can be loaded again through I/O write instructions, or if list chaining is enabled, it is reloaded automatically by the hardware from the list table entry in memory. The LAR entry in memory must always contain an even-aligned address (that is, LA0=0). The LAR register is always incremented by two, following the movement of one of the list table entries; this new value is present if the descriptor block is read.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
|LA15|LA14|LA13|LA12|LA11|LA10|LA9|LA8|LA7|LA6|LA5|LA4|LA3|LA2|LA1|LA0|
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
This register contains the upper five address bits of a pointer into memory where a table exists to update a channel's descriptor block. It must contain a physical address, and be loaded initially through an I/O write instruction. After initialization, it optionally can be loaded again through I/O write instructions, or if list chaining is enabled, it is reloaded automatically by the hardware from the list table entry in memory. It is always incremented following the movement of one of the list table entries, and this new value is present if the descriptor block is read.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+----+----+----+----+----+
|XX|XX|XX|XX|XX|XX|XX|XX|XX|XX|XX|LA20|LA19|LA18|LA17|LA16|
+--+--+--+--+--+--+--+--+--+--+--+----+----+----+----+----+
This register contains the 16-bit value that determines the number of DMA cycles to occur until a terminal count (count = 0) condition exists. Upon reaching terminal count, many options exist, depending on the state of the CCW. (See "Channel Control Word (CCW)" for additional information.) A value of 0000h loaded into this register causes 65536 transfers to occur before terminal count.
MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
|TC15|TC14|TC13|TC12|TC11|TC10|TC9|TC8|TC7|TC6|TC5|TC4|TC3|TC2|TC1|TC0|
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
This register contains two bytes of data that are accessed when the C1 and C2 bits of the CCW enable the character matching logic for one of three modes. (See "Channel Control Word (CCW)" for additional information.)
MSB LSB MSB LSB
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
|CM15|CM14|CM13|CM12|CM11|CM10|CM9|CM8|CM7|CM6|CM5|CM4|CM3|CM2|CM1|CM0|
+----+----+----+----+----+----+---+---+---+---+---+---+---+---+---+---+
There are two types of list chaining: buffer and linked.
The co-processor adapter BM DMA controller supports a feature known as buffer list chaining (BLC) or scatter/gather DMA. This feature allows the programmer to create, in memory, lists of different data buffer areas and buffer counts. The contents of the lists can be reloaded automatically to the CDB after a terminal count, character match, or an end-of-message condition for the present data buffer occurs. The channel optionally can interrupt or not interrupt the 80C186 when any of these conditions occurs. Also, the DMA channel can be stopped independently or allowed to continue at this point. In addition, certain control information in the CCR can be changed on-the-fly, which allows for dynamic changing of DMA parameters.
A 21-bit address pointer to the list in memory is maintained within the CDT. If list chaining is enabled at the time of terminal count, character match, or an end-of-message condition, the hardware does two memory writes, followed by four memory reads, starting at this memory address. It stores the present transfer count and the present DUSCC receiver status byte, and then fetches four new words of CDT.
At the end of this operation,
the list address pointer in the CDT is
pointing to an address equal to the previous address, + C.
This address is the start of the next list in the chain.
This provides a mechanism
to offload the 80C186 from processing the DMA terminal count,
character match, or end-of-message interrupts.
In theory, this list of buffers could occupy any amount of free
contiguous memory.
Buffer list chaining is shown in Figure 25..
Figure 25. CDT Buffer List Chaining (Receive DMA Channel)
Channel Descriptor Table (CDT) Memory
0 15
+--------------------------+
List Address Pointer (LAP) ----->| Transfer Count Store |
(Always even-address aligned) +--------------------------+
| Receive Status Store | LAP + 2
+--------------------------+
| New Transfer Count | LAP + 4
+--------------------------+
| New Target Address | LAP + 6
+--------------------------+
| New Target Address Ext | LAP + 8
+--------------------------+
| New Channel Control Word | LAP + A
+--------------------------+
| Start of Next List | LAP + C
+--------------------------+
Figure 25. shows how a chain table is set up in memory for a receive DMA channel. If the DMA channel is set up for transmit, the table is the same, except that the DMA does not store the first two status words before reading the new CDT information. A receive BLC table occupies six memory words and a transmit BLC table entry occupies four memory words.
In addition to BLC described above, the hardware provides a mechanism to allow these lists of buffer information to occupy non-contiguous areas of memory and be dynamically linked through information present in the list. This is known as linked list chaining (LLC), which is a special case of BLC.
When a terminal count, a character match, or an end-of-message condition
occurs and list chaining is enabled,
the first memory fetch (equals 0000h)
causes the hardware to fetch five
additional 16-bit words, instead of
three additional words as in BLC.
This technique is detailed in Figure 26..
Figure 26. Link List Chaining (Receive DMA Channel)
Channel Descriptor Table (CDT) Memory
0 15
+-----------------------------+
List Address Pointer (LAP) ----->| Transfer Count Store |
(Always even-address aligned) +-----------------------------+
| Receive Status Store | LAP + 2
+-----------------------------+
| 0000h (LLC Indicator) | LAP + 4
+-----------------------------+
| New Transfer Count | LAP + 6
+-----------------------------+
| New Target Address | LAP + 8
+-----------------------------+
| New Target Address Ext | LAP + A
+-----------------------------+
| New Channel Control Word | LAP + C
+-----------------------------+
| New List Address Pointer Ext| LAP + E
+-----------------------------+
| New List Address Pointer | LAP + 10h
+-----------------------------+
Figure 26. shows how a chain table is set up in memory for a receive DMA channel. If the DMA channel is set up for transmit, the table is the same, except that the DMA does not store the first two status words before reading the new CDT information. Hence, a receive LLC table occupies nine memory words and a transmit LLC table entry occupies seven memory words.
At the end of this operation, the CDT contains a new pointer to a new list located anywhere else in memory. The two options of BLC and LLC can be combined to create circular buffers that have any number of buffer areas.
Due to the nature of the DMA/peripheral interface chip logic and the DUSCC interrupt structure, certain programming steps must be adhered to when using the LC EOM feature. These are outlined below.
The LC EOM option of DMA/peripheral interface chip allows for a tight coupling of the DUSCC chip with the DMA/peripheral interface chip, while processing synchronous protocol data frames. The DUSCC chip outputs a signal, EOPN, concurrent with the last byte of a data frame that is transferred from the DUSCC to memory by the DMA/peripheral interface chip DMA. The DMA/peripheral interface chip uses this signal to start either a list or linked-list buffer chaining operation. During this operation, the DMA/peripheral interface chip reads the DUSCC receiver status register (RSR), and then writes back to this register to clear all active status bits. The DMA/peripheral interface chip stores the RSR value at a known location in memory.
The consideration to the programmer involves which EOM interrupt bit should be enabled when using the LC EOM feature. The DUSCC contains an option in its interrupt enable register (IER) to enable EOM interrupts; this is bit 3 in the IER. This bit also enables interrupts when the abort sequence is detected. If it is desired that abort interrupts be enabled (which would be the typical case), then EOM interrupts also are enabled automatically since they share the same enable bit in the IER.
Also, the DMA/peripheral interface chip contains an option in its CCW to enable EOM interrupts when it detects the EOPN signal from the DUSCC. Use the following table to determine the interrupt option desired.
End-of-Message Interrupting Options with LC EOM Enabled
+-----------------+------------------+------------------------+
| Echo EOM Enable | DUSCC EOM Enable | # Interrupts Generated |
Case | Bit in CCW | Bit in IER | for EOM Condition |
+-----------------+------------------+------------------------+
(1) | Not set | Not set | 0 |
| | | |
(2) | Set | Not set | 1 |
| | | |
(3) | Set | Set | 1 or 2 |
| | | |
(4) | Not set | Set | Invalid option |
+-----------------+------------------+------------------------+
End-of-Message Interrupting Options with LC EOM Enabled
+-----------------+------------------+------------------------+
| Echo EOM Enable | DUSCC EOM Enable | # Interrupts Generated |
Case | Bit in CCW | Bit in IER | for EOM Condition |
+-----------------+------------------+------------------------+
(1) | Not set | Not set | 0 |
| | | |
(2) | Set | Not set | 1 |
| | | |
(3) | Set | Set | 1 or 2 |
| | | |
(4) | Not set | Set | Invalid option |
+-----------------+------------------+------------------------+
Since it is possible for an FFh interrupt to be returned, the program must include an interrupt handler for this condition. This handler should issue the 80C186 EOI command, but not try to gather any interrupt-specific information. The FFh interrupt handler is included in IBM's Realtime Control Microcode (RCM).
The CDT contains a 2-byte entry, the CMR, which is used to recognize characters that are in-bound to memory from a DMA receive channel. A match of this data can be one of three types:
Each of the 16 DMA channels has three possible sources of interrupts to the 80C186. These 48 possible different interrupts are accommodated by one of two programmable options: single interrupt vectors and multiple interrupt vectors.
The first option is a single interrupt vector, coupled with a primary status and secondary status register. With this option, a single vector is programmed into the DMAVECTOR register, and this vector is returned for any of the 48 possible interrupts. The software then reads the primary status register (bits 4-7 of the DMASSIGN register), and this returns the channel number of the interrupt. The software then reads the secondary status register (DMASTAT) associated with that channel to determine the source of the interrupt within the channel.
The second option is for multiple vectors, coupled with a single-level status register. With this option, 16 different vectors can be returned after an interrupt. The vector returned is from the interrupting channel. Therefore, only a read of the DMASTAT register is necessary to fully characterize the source of the interrupt. The status registers and the vector registers are detailed in following sections.
The 16 interrupt vectors are prioritized as a daisy chain, with one of two priority settings established according to bit 1 of the DMASSIGN register. However, all of these interrupts share a single physical interrupt line to the 80C186. Therefore, any channel interrupt subroutine can interrupt any other channel interrupt subroutine, provided the 80C186 EOI command has been issued to its interrupt controller. The daisy chaining of the interrupt vectors is at the channel level. If all channels have interrupts pending, level 0 is acknowledged first. If level 0 gets another interrupt condition before any of the lower-level channels are acknowledged, level 0 is acknowledged again, before other pending interrupts.
Also, the 80C186 EOI command should not be issued until after the status register for that channel is read. This read resets the physical interrupt line for that channel, and clears all active status bits.
Each DMA channel has a DMA status register (DMASTAT) associated with it. This register is cleared when it is read. Also, the physical interrupt line is reset by this read. Since three conditions can cause the interrupt, it is possible for multiple conditions to be present when the status register is read. However, since the register and interrupt line are cleared by the read, only one interrupt is presented to the 80C186. Therefore, the interrupt service routine must be capable of servicing all the possible interrupt sources. The 80C186 EOI command should not be issued until after the status register is read.
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| XX| XX| XX| XX| XX| EOM| TC| CM|
+----+----+----+----+----+----+----+----+
Bit 0, Character Match Status
When this bit is set to 1,
it indicates that a character match of the type specified
in CCW bits 8 and 9 has occurred since the last read of the DMASTAT.
Bit 1, Terminal Count Status
When this bit is set to 1, it indicates that
a 0001h-to-0000h transition of the CDT
TCR has taken place since the last read of the DMASTAT.
This bit is set even if these interrupts are disabled in the CCW.
Bit 2, End-of-Message Status
When this bit is set to 1, it indicates
an end-of-message condition has occurred
in the DUSCC since the last read of the DMASTAT.
This bit is reset if these interrupts are disabled in the CCW.
If this bit is set to 1,
an ECHOEOI to the appropriate command port must precede
the 80C186 EOI.
Bits 3-7
These bits are don't care.
This register is used to assign different operating modes for the DMA/peripheral interface chip. It is an 8-bit read/write register located at 8212h.
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| CH3| CH2| CH1| CH0|RSVD| AS2| AS1| AS0|
+----+----+----+----+----+----+----+----+
Bit 0, AS0
When this bit is set to 1,
it assigns two DMA channels per transmit and receive port for the
first four ports. In this mode, the following chart applies:
DMA
Channel Services DMA Requests for
-------- -------------------------
0 & 8 Receive Port 0
1 & 9 Transmit Port 0
2 & 10 Receive Port 1
3 & 11 Transmit Port 1
4 & 12 Receive Port 2
5 & 13 Transmit Port 2
6 & 14 Receive Port 3
7 & 15 Transmit Port 3
When this bit is reset to 0, it assigns one DMA channel
per transmit and receive port for eight ports.
Bit 1, Receive/Transmit Interrupt Priority Select
This bit selects whether all receive channels interrupt on a higher
priority than transmit channels, or whether the channel number
determines the interrupting priority. When this bit is set to 1,
it selects the
priority from highest to lowest as follows: REC0, REC1, REC2, ...
TR14, TR15. When this bit is reset to 0,
it selects the priority from highest to lowest as
follows: REC0, TR0, REC1, TR1, REC2, ... REC15, TR15.
Bit 2, Vector Mode Select
This bit selects whether the vector
presented to the 80C186 is a single vector, or 1 of 16
vectors that have the interrupting channel information encoded within
the vector. When this bit is set to 1, it selects the single vector
mode. When this bit is reset to 0, it selects the multiple vector mode.
Bit 3, Reserved
This bit is reserved.
Bits 4-7, Encoded Channel Number
These bits are read-only, and
are valid only if bit 2 is set to 1 and an interrupt has occurred.
The interrupting channel number is encoded with bit 7 as the MSB
and bit 4 as the LSB.
This register is accessed during an 80C186 interrupt acknowledge cycle. It places the 8-bit vector on the bus the 80C186 uses to point to the address in memory of an interrupt subroutine. Depending on the vector mode that is programmed in the DMAASSIGN register, this vector either:
For case 2, the interrupt subroutine then reads the upper four bits of the DMAASIGN register to determine the interrupting DMA channel.
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| VB7| VB6| VB5| VB4| VB3| VB2| VB1| VB0|
+----+----+----+----+----+----+----+----+
Note: This register is a 4-bit I/O write at 8210h, and a 4-bit I/O read at 8210h. Only VB7, VB6, VB5, and VB0 are read and write. VB1-VB4 are defined only during the interrupt acknowledge cycle of the 80C186.
The interrupt priority logic ensures the correct vector is supplied for the highest-priority pending interrupt.
Bits 0 and 5-7
These bits are programmed at initialization to a base vector value.
This means the register can supply
any 16 consecutive even-valued vectors or 16
consecutive odd-valued vectors.
Bits 1-4
In the multiple vector mode,
these bits are set by hardware and are binary encoded to supply
the DMA channel number of the interrupt source.
For example:
4 3 2 1 Channel
+--+--+--+--+--------+
| 0| 0| 0| 0| 0 |
+--+--+--+--+--------+
| 0| 0| 0| 1| 1 |
+--+--+--+--+--------+
| 1| 1| 1| 1| 15 |
+--+--+--+--+--------+
In single-vector mode, these bits are part of the single base vector.
This register allows all DMA channels to be disabled with one command. The command can take either of two modes, depending on how critical is the code path to be executed.
The first mode is the write mode. In this mode, a 1 is written to the register to stop all channels, and a 0 is written to restart all channels. There can be from 1 to 16 DMA requests pending within the DMA/peripheral interface chip at the time the register bit is set to 1 by the I/O write from the 80C186. If any requests were pending, they are serviced immediately, before the code is run. Therefore, critical code paths can be affected.
The second mode is the read mode. In this mode, the executing program must poll the register bit. If it reads a 1 when polled, no internal DMA requests are pending and all subsequent DMA requests are disabled; the critical code will run uninterrupted by DMA activity. All channels are re-enabled by writing a 0 back to the register. If it reads a 0 when polled, 1 or more internal DMA requests are pending and no channel disabling action is taken. The register must be re-polled if channel disabling still is required.
For either the write or the read mode, the disabled state of the channels is not reflected in the ENABLE/DISABLE bit of the CCW. The DMADISABLE register is 8-bit read/write at 8214h.
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| X | X | X | X | X | X | X | DIS|
+----+----+----+----+----+----+----+----+
Bit 0, DIS
This bit is a writable status bit. If this bit is set to 1,
all channels are stopped. If this bit is reset to 0,
all channels are re-enabled.
If this bit is read as 1, no internal DMA requests are
pending and all channels are stopped.
If this bit is read as a 0, from 1 to 16
DMA requests are pending internally and no disabling action is taken.
Bits 1-7, Reserved
These bits are always read as 0s.
Figure 27. shows
the I/O register map for the CDT and the DMASTAT registers.
The CDT registers are 16-bit read/write and should only be accessed on
even boundaries with a 16-bit I/O instruction.
The DMASTAT registers are 8-bit, read-only.
Figure 27. I/O Register Map for CDT and DMASTAT
+-------------+-----------------+-----------------+ | DMA Channel | CDT Address | DMASTAT Address | +-------------+-----------------+-----------------+ | 0 | 8000h - 800Eh | 8200h | | 1 | 8020h - 802Eh | 8201h | | 2 | 8040h - 804Eh | 8202h | | 3 | 8060h - 806Eh | 8203h | | 4 | 8080h - 808Eh | 8204h | | 5 | 80A0h - 80AEh | 8205h | | 6 | 80C0h - 80CEh | 8206h | | 7 | 80E0h - 80EEh | 8207h | | 8 | 8100h - 810Eh | 8208h | | 9 | 8120h - 812Eh | 8209h | | 10 | 8140h - 814Eh | 820Ah | | 11 | 8160h - 816Eh | 820Bh | | 12 | 8180h - 818Eh | 820Ch | | 13 | 81A0h - 81AEh | 820Dh | | 14 | 81C0h - 81CEh | 820Eh | | 15 | 81E0h - 81EEh | 820Fh | +-------------+-----------------+-----------------+
The performance of the DMA channels is more accurately described in the context of the line speeds that are supported. This discussion focuses on the limits of the DMA hardware, and what affect these limits have on the bandwidth of the 80C186. No statement is made as far as the software implication on bandwidth.
The structure of the DMA arbiter logic ensures that at supported data rates, the 80C186 is able to perform, on average, one cycle for every cycle the DMA has control of the local bus.
On average, an 80C186 cycle is one wait state, or five clocks. Also, every I/O cycle is fixed at three wait states. It takes three idle clocks for the DMA cycle to start after the local bus is granted to the DMA controller.
This information, and the fact an 80C186 clock cycle is
80 ns at 12.5 MHz, allows the information outlined in
Figure 28. to be derived.
Figure 28. Local Bus Utilization
+---------------------+-----------+---------------------+-----------+-- - - - | 80C186 memory cycle | DMA cycle | 80C186 memory cycle | DMA cycle | | 5 clocks | 15 clocks | 5 clocks | 15 clocks | Etc | 400 ns | 1200 ns | 400 ns | 1200 ns | +---------------------+-----------+---------------------+-----------+-- - - -
A DMA cycle is possible every 400 ns + 1200 ns = 1600 ns.
Each DMA cycle moves one byte, or eight bits off the line. Therefore, 1/1600 ns = 625 kilobytes/second are movable from the DUSCC chip to memory, or vice versa. This is equivalent to a 5.0 megabits/second aggregate data rate for all channels. At this rate, the 80C186 is executing every 5 of 20 clocks, or 25% of the total bus bandwidth. The DMA owns 75% of the bus bandwidth.
To support eight duplex lines at 64 kilobits/second, an aggregate data rate of 128 kilobytes/second is required. This equals one byte every 8 &usec.; or, equivalently, the DMA usage is 15 of 100 clocks, or 15%.
Applying this calculation to a 2.048 megabits/second, duplex data rate yields a DMA bandwidth usage of 65%, meaning the 80C186 is processing only 35% of its possible time. So, with one channel running 2.048 megabits/second, duplex, the effective clock rate of the 80C186 is 4.3 MHz.
The Adapter Description File (ADF) provides a software solution to a hardware problem for the co-processor adapter. The Guide to Operations for the IBM Realtime Interface Co-Processor Portmaster Adapter/A includes an Adapter Description File diskette and instructions on its use. A menu of options regarding the following is included:
The co-processor adapter implements six Programmable Option Select (POS) registers to support automatic configuration. Eight bits (FE, AB0, AB1, AB2, AB3, DP, CKS, and CKI) are architected by the Micro Channel. The remaining bits are used to configure the co-processor adapter hardware. All the bits are mapped to other system unit and co-processor adapter I/O read/write registers.
+--+--+--+--+--+--+--+--+ |D7|D6|D5|D4|D3|D2|D1|D0| ++-++-++-++-++-++-++-++-+ | | | | | | | | | | | | | | | | POS0 POS1 POS2 POS3 POS4 POS5 | | | | | | | | | | | | | | | +-- 0 1 SE A13 A21 FE | | | | | | +----- 0 1 L1 A14 A22 AB0 | | | | | +-------- 0 1 L2 A15 A23 AB1 | | | | +----------- 0 1 L4 A16 A30 AB2 | | | +-------------- 1 0 C1 A17 A31 AB3 | | +----------------- 1 0 C2 A18 W1 RSVD | +-------------------- 1 0 C4 A19 W2 CKS +----------------------- 0 1 RSVD A20 W4 CKI
POS0 and POS1 form the ID (8F70h) for the co-processor adapter. These bits are not controlled by the Adapter Description File. The system unit Setup Program uses this ID to identify that a co-processor adapter card is installed.
All eight POS2 bits are mapped into INITREG0.
This bit is defined in the Micro Channel to disable the attachment card from the system unit bus when cleared. It is cleared on a channel reset. The SE bit normally is used only by the System Setup Program. Use this bit with caution.
These bits determine the interrupt level of the co-processor adapter within the system unit environment.
These bits specify the system unit base I/O address for all I/O registers. Each card should have a unique address, compared with each other and any other attachment card in the system unit.
This bit is reserved.
All eight bits of POS3 are mapped into LOCREG0.
These bits indicate where the user wants the co-processor adapter to be located within the system unit's memory map:
Bits D0-4 of POS4 are mapped into LOCREG1; the other three bits (D5-7) select the window size.
These bits are a continuation of POS3. Program the value that corresponds to the desired location for the co-processor adapter with the system unit's memory map.
This value selects the window size that the co-processor adapter views at any one time. 8KB is the default. All other values are reserved.
Bits D0-4 of POS5 are mapped into INITREG3. Bit D0 enables and disables the fairness feature of the system unit's arbitration bus. Bits D1-4 determine the arbitration level that the co-processor adapter will operate on within the system unit environment. Bit D5 is reserved. Bit D6 (I/O channel check status) is architected by the Micro Channel, but will always be set to 1. Bit D7 (I/O channel check indicator) indicates that a channel check has occurred.
This chapter discusses the following components, which provide electrical interfaces between the co-processor adapter and external devices:
The co-processor adapter card can accommodate one pluggable interface board at a time. Each interface board converts TTL compatible signals to (or from) standard EIA or CCITT electrical signal compatibility, and provides the physical means for external communication using various protocols.
Specific details of each type of optional interface board are discussed individually in their respective chapter, starting with Chapter 4.
The electrical interfaces include signals between the co-processor adapter and the optional interface boards. The interface boards are modular, and mount onto the co-processor adapter to provide electrical interfaces to external devices that conform to the previously mentioned protocol standards.
Up to four, dual universal serial communications controllers (DUSCC) are supported by one co-processor adapter. Two DUSCCs are on the co-processor adapter and up to two DUSCCs can reside on the interface board, depending on which type of interface board is attached to the co-processor adapter.
The interface boards connect electrically to the co-processor adapter card through multipin connector strips (K0, K1, and K2) mounted on the boards. Each interface board is secured physically to the co-processor adapter card by two plastic stand-offs.
Interface Board Layout
+---------------------------------------------------+
| +-------------------------------+ +--+--+-+
+-+----+ | | |..|..|.|
+-+ | | | |..|..|.|
| |Multi-| | | |..|..|.| Two 60-pin
| |pin | | SCCs, drivers, receivers, | |..|..|.| connectors
| |conn | | and discrete components | |..|..|.| (K1 and K2)
| |K9B | | | |..|..|.|<--------
| | | | | |..|..|.| One 30-pin
+-+ | | | |..|..|.| connector
+-+----+ +-------------------------------+ |..|..|.| (K0)
+-------------------------------------------+--+--+-+
K2 K1 K0
K2 K1 K0
+-----+-----+--+
|02 01|02 01|01|
|04 03|04 03|02|
|06 05|06 05|03|
|08 07|08 07|04|
| . .| . .| .|
Connector Strip | . .| . .| .|
Pin Designations | . .| . .| .|
| . .| . .| .|
| . .| . .| .|
| | | |
|56 55|56 55|28|
|58 57|58 57|29|
|60 59|60 59|30|
+-----+-----+--+
The co-processor adapter supports a one-byte interface board ID at either address 86h or 0E000h. If an ID exists at 86h (a non-FFh value), it is assumed that no interface board ROS exists for this board.
The co-processor adapter uses up to 4KB of interface board ROS to supply the Realtime Control Microcode with specific information about the interface board. This ROS resides in the 80C186 I/O address space at 0E000h-0EFFFh, and is readable by the 80C186 DMA or by I/O read instructions. All optional interface boards must have this ROS.
The data contained in the interface board ROS consists of eight sections:
Table 11. I/O Address Map Field
+----------+----------+-----------------------+-----------------------------+ | I/O | Length | Field | Comments | | Address | Bytes | | | | (hex) | (hex) | | | +----------+----------+-----------------------+-----------------------------+ | E000h | 1F | Interface board header| | +----------+----------+-----------------------+-----------------------------+ | E01Fh | 10 | Hardware information | | | | | for ports residing on | | | | | the interface board | | +----------+----------+-----------------------+-----------------------------+ | E02Fh | 2n | Tx and Rx DMA | n = Maximum number of DUSCC | | | | channel numbers | ports possible (20h) | +----------+----------+-----------------------+-----------------------------+ | E06Fh | 18 | CIO data direction | | | | | register information | | +----------+----------+-----------------------+-----------------------------+ | E087h | 2n | Pointers to port | n = Number of DUSCC ports | | | | information | installed on the base card | | | | | and on the interface board | +----------+----------+-----------------------+-----------------------------+ | | 3Dn | Port information | n = Number of DUSCC ports | | | | | installed on the base card | | | | | and on the interface board | +----------+----------+-----------------------+-----------------------------+ | E867h | Variable | Read cable ID routine | See the appropriate section | +----------+----------+-----------------------+-----------------------------+ | EFFEh | 2 | Interface board ROS | | | | | checksum | | +----------+----------+-----------------------+-----------------------------+
Table 12. Interface Board Header Field
+----------+-----------------------------+------------------------------------+ | Offset | Description | Comments | | (hex) | | | +----------+-----------------------------+------------------------------------+ | 00h | Interface board ROS ID | | +----------+-----------------------------+------------------------------------+ | 01h | Interface board ROS | | | | presence | | | | | 00h | | | | = ROS conforms to RCM LCLS * | | | | 01h | | | | = ROS does not conform to RCM LCLS | +----------+-----------------------------+------------------------------------+ | 02h | Interface board ROS level | | +----------+-----------------------------+------------------------------------+ | 03h | Port count | Total number of ports | | | | (base card + interface board) | +----------+-----------------------------+------------------------------------+ | 04h-1Eh | Copyright notice | '(C) COPYRIGHT IBM CORP 1989' | +----------+-----------------------------+------------------------------------+* RCM LCLS is an abbreviation for Realtime Control Microcode Logical Control Line Services.
Table 13. Hardware Information for Ports Residing on Interface Board Field
+----------+-----------------------------+------------------------------------+ | Offset | Description | Comments | | (hex) | | | +----------+-----------------------------+------------------------------------+ | 00h | Interface board port count | Number of ports on interface board | +----------+-----------------------------+------------------------------------+ | 01h-02h | Communications controller | CC15 . . . . . . . . . . . CC1 CC0 | | | (CC) presence on the | One bit per CC: | | | interface board | | | | | 0h = CC not present | | | | 1h = CC present | +----------+-----------------------------+------------------------------------+ | 03h | CIO presence on the | C7 C6 C5 C4 C3 C2 C1 C0 | | | interface board | One bit per CIO: | | | | | | | | 0h = CIO not present | | | | 1h = CIO present | +----------+-----------------------------+------------------------------------+ | 04h-07h | Sync capability | One bit per port | | | | | | | | 0h = Sync not present | | | | 1h = Sync present | +----------+-----------------------------+------------------------------------+ | 08h-0Fh | Type of communications | Two bits per port | | | controller | | | | | 00h = Reserved | | | | 01h = DUSCC | | | | 10h = Reserved | | | | 11h = Extended Type | | | | | | | | (see next eight bytes for CC Type) | +----------+-----------------------------+------------------------------------+
Table 14. Tx and Rx DMA Channel Numbers Field
+----------+-----------------------------+--------------------------------------+ | Offset | Description| Comments | | (hex) | | | +----------+------------+-------------------------------------------------------+ | 00h - | DMA channel| One byte per port | | (n-1)h | number for | | | | Tx | n | | | | = Number of ports on the interface board | | | | 00h-FDh | | | | = Channel number for Tx | | | | FEh | | | | = Only one DMA channel per port (configurable) | | | | FFh | | | | = No DMA for Tx | +----------+------------+-------------------------------------------------------+ | nh - | DMA channel| One byte per port | | (2n-1)h | number for | | | | Rx | n | | | | = No. of ports on the interface board | | | | 00h-FDh | | | | = Channel number for Rx | | | | FFh | | | | = No DMA for Rx | | | | | | | | = If Tx DMA = FEh, Rx DMA is the channel number of the| | | | configurable channel | +----------+------------+-------------------------------------------------------+ | 2nh-3Fh | Filler | This field should be filled with 0s; it will be | | | | present only when the number of ports on the interface| | | | board is less than the maximum number of DUSCC ports | | | | possible (20h) | +----------+------------+-------------------------------------------------------+
Table 15. Data Direction Register Information Field
+----------+-----------------------------+--------------------------------------+ | Offset | Description | Comments | | (hex) | | | +----------+-----------------------------+--------------------------------------+ | 00h | CIO 0 port A data direction | One bit per control signal | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+ | 01h | CIO 0 port B data direction | One bit per control signal | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+ | 02h | CIO 0 port C data direction | One bit per control signal | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+ | 03h | CIO 1 port A data direction | One bit per control signal | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+ | 04h | CIO 1 port B data direction | One bit per control signal | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+ | 05h | CIO 1 port C data direction | One bit per control signal | | . | . | | | . | . | 0 = Output | | . | . | 1 = Input | | | | | | | | . | | | CIO 7 port C data direction | . | | 17h | | . | | | | One bit per control signal: | | | | | | | | 0 = Output | | | | 1 = Input | +----------+-----------------------------+--------------------------------------+
Table 16. Pointers to Port Information Field
+----------+-----------------------------+-------------------------------+ | Offset | Description | Comments | | (hex) | | | +----------+-----------------------------+-------------------------------+ | 00h | Pointer to 1st port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 02h | Pointer to 2nd port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 04h | Pointer to 3rd port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 06h | Pointer to 4th port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 08h | Pointer to 5th port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 0Ah | Pointer to 6th port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 0Ch | Pointer to 7th port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+ | 0Eh | Pointer to 8th port | See the appropriate section | | | information | . | | . | . | . | | . | . | . | | . | . | | | (2x-1)h | Pointer to nth port | See the appropriate section | | | information | | +----------+-----------------------------+-------------------------------+
Table 17. Port Information Field
+----------+--------------------------------------------+--------------------+ | Offset | Description | Comments | | (hex) | | | +----------+--------------------------------------------+--------------------+ | | For each port on the interface board, the | | | | appropriate section is repeated | | +----------+--------------------------------------------+--------------------+
Table 18. Read Cable ID Routine Field
+----------+--------------------------------------------+--------------------+ | Offset | Description | Comments | | (hex) | | | +----------+--------------------------------------------+--------------------+ | 00h-01h | Length of routine | Length is in bytes | +----------+--------------------------------------------+--------------------+ | 02h | Routine to read the cable ID | | | | and convert it into the | | | | interface type identifier for each port | | +----------+--------------------------------------------+--------------------+
Note:
This field is optional.
Table 19. Interface Board Checksum Field
+----------+--------------------------------------------+--------------------+ | Offset | Description | Comments | | (hex) | | | +----------+--------------------------------------------+--------------------+ | 00h | Two-byte checksum, with the | | | | most-significant bits at offset 0FFFh and | | | | the least-significant bits at offset 0FFEh.| | +----------+--------------------------------------------+--------------------+
Table 20. Port X Information Field
+--------+------------+--------------------+----------------------------------+ | Offset | Field Name | Description | Comments | | (hex) | | | | +--------+------------+--------------------+----------------------------------+ | 00h | PORT_NUMBER| CC port number | CC is an abbreviation for serial | | | | | communications controller | +--------+------------+--------------------+----------------------------------+ | 01h | INT_TYPE | Interface Type | 00h = RS-232-D | | | | | 01h = RS-422-A | | | | | 02h = Reserved | | | | | 03h = Reserved | | | | | 04h-FDH = Reserved | | | | | FEh = Interface unknown | | | | | FFh = Configurable by cable | +--------+------------+--------------------+----------------------------------+ | 02h-03h|LCLS_SUPPORT| Indicates which | Not currently supported | | | | LCLS services are | | | | | supported | | +--------+------------+--------------------+----------------------------------+ | 04h-05h| HRS(OUT) | Port address | For all entries below, the CIO | | | PORT_ADDR | or CIO | port numbering scheme is as | | | | number if port | follows. | | | | type = 00h or 01h | | | | | | | | | | | | | | | | 0h = CIO0, port A | | | | | 1h = CIO0, port B | | | | | 2h = CIO1, port A | | | | | 3h = CIO1, port B | | | | | 4h = CIO1, port C | | | | | 5h = CIO2, port A | | | | | 6h = CIO2, port B | | | | | 7h = CIO2, port C | | | | | . | | | | | . | | | | | . | | | | | 16h = CIO7, port C | +--------+------------+--------------------+----------------------------------+ | 06h | HRS(OUT) | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 07h | HRS(OUT) | Describes device | 00h = Port A or Port B | | | PORT_TYPE | that controls | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | FFh = HRS(OUT) not supported | +--------+------------+--------------------+----------------------------------+ | 08h | HRS(OUT) | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used to | HRS(OUT); output logic 1 to | | | | control this signal| deactivate | | | | | 01h = Output logic 1 to activate | | | | | HRS(OUT); output logic 0 to | | | | | deactivate | +--------+------------+--------------------+----------------------------------+ | 0Bh | TXBLK | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 0Ch | TXBLK | Describes device | 00h = Port A or Port B of CIO | | | PORT_TYPE | that control | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | FEh = RTS is required to enable | | | | | transmit | | | | | | FFh = TXBLK not supported | +--------+------------+--------------------+----------------------------------+ | 0Dh | TXBLK | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used to | TXBLK; output logic 1 to | | | | control this signal| deactivate | | | | | 01h = Output logic 1 to activate | | | | | TXBLK; output logic 0 to | | | | | deactivate | +--------+------------+--------------------+----------------------------------+ | 0Eh-0Fh| CLOCK | Port address or CIO| | | | PORT_ADDR | port number if port| | | | | type = 00h or 01h | | +--------+------------+--------------------+----------------------------------+ | 10h | CLOCK | Register bit | | | | BIT_NO | position for this | | | | | signal | | +--------+------------+--------------------+----------------------------------+ | 11h | CLOCK | Describes device | 00h = Port A or Port B of CIO | | | PORT_TYPE | that controls | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | FFh = CLOCK not supported | +--------+------------+--------------------+----------------------------------+ | 12h | CLOCK | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used to | DTE CLK; | | | | control this | 01h = Output logic 1 to activate | | | | signal | DTE CLK; | | | | | output logic 0 to activate DCE | | | | | CLK | +--------+------------+--------------------+----------------------------------+ | 15h | RTS | Register bit | This field is not used if the | | | BIT_NO | position for | signal is from the CC | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 16h | RTS | Describes device | 00h = Port A or Port B of CIO | | | PORT_TYPE | that control | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | 03h = DUSCC | | | | | FFh = RTS not supported | +--------+------------+--------------------+----------------------------------+ | 17h | RTS | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used | RTS; output logic 1 to deactivate| | | | to control | 01h = Output logic 1 to activate | | | | this signal | RTS; | output logic 0 to | | | | | deactivate | +--------+------------+--------------------+----------------------------------+ | 18h-19h| DTR | Port address or CIO| This field is not used if the | | | PORT_ADDR | port number if port| signal is from the CC | | | | type = 00h or 01h | | +--------+------------+--------------------+----------------------------------+ | 1Ah | DTR | Register bit | This field is not used if the | | | BIT_NO | position for | signal is from the CC | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 1Bh | DTR | Describes device | 00h = Port A or Port B of CIO | | | PORT_TYPE | that controls | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | 03h = DUSCC | | | | | FFh = DTR not supported | +--------+------------+--------------------+----------------------------------+ | 1Ch | DTR | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used | DTR; output logic 1 to deactivate| | | | to control | 01h = Output logic 1 to activate | | | | this signal | DTR; | | | | | output logic 0 to deactivate | +--------+------------+--------------------+----------------------------------+ | 1Dh-1Eh| CONTROL | Port address or CIO| | | | PORT_ADDR | port number if port| | | | | type = 00h or 01h | | +--------+------------+--------------------+----------------------------------+ | 20h | CONTROL | Describes device | 00h = Port A or Port B of CIO | | | PORT_TYPE | that controls | 01h = Port C of CIO | | | | this signal | 02h = Any 8-bit read/write | | | | | register | | | | | FFh = CONTROL not supported | +--------+------------+--------------------+----------------------------------+ | 21h | CONTROL | Describes logical | 00h = Output logic 0 to activate | | | ACTIVATION | level used | CONTROL; output logic 1 to | | | | to control | deactivate | | | | this signal | 01h = Output logic 1 to activate | | | | | CONTROL; output logic 0 to | | | | | deactivate | +--------+------------+--------------------+----------------------------------+ | 22h | RI | CIO port number | 00h-16h = CIO port number | | | PORT_NO | | FFh = RI not supported | +--------+------------+--------------------+----------------------------------+ | 23h | RI | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 24h | RI | Describes | 00h = RI is active when read | | | ACTIVATION | logical level | logic 0; RI is not active when | | | | used to control | read logic 1 | | | | this signal | 01h = RI is active when read | | | | | logic 1; RI is not active when | | | | | read logic 0. | +--------+------------+--------------------+----------------------------------+ | 25h | HRS(IN) | CIO port number | 00h-16h = CIO port number | | | PORT_NO | | FFh = HRS(IN) not supported | +--------+------------+--------------------+----------------------------------+ | 26h | HRS(IN) | Register bit | | | | BIT_NO | postion for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 27h | HRS(IN) | Describes logical | 00h = HRS(IN) is active when read| | | ACTIVATION | level used to | logic 0; HRS(IN) is not active | | | | control this | when read logic 1. | | | | signal | 01h = HRS(IN) is active when read| | | | | logic 1; HRS(IN) is not active | | | | | when read logic 0 | +--------+------------+--------------------+----------------------------------+ | 28h | CTS | Port Number for CTS| 00h-16h = CIO port number | | | PORT_NO | | FEh = From CC | | | | | FFh = CTS not supported | +--------+------------+--------------------+----------------------------------+ | 29h | CTS | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 2Ah | CTS | Describes logical | 00h = CTS is active when read | | | ACTIVATION | level used to | logic 0; CTS is not active when | | | | control this | read logic 1 | | | | signal | 01h = CTS is active when read | | | | | logic 1; CTS is not active when | | | | | read logic 0 | +--------+------------+--------------------+----------------------------------+ | 2Bh | DCD | CIO port number | 00h-16h = CIO port number | | | PORT_NO | | FEh = From CC | | | | | FFh = DCD not supported | +--------+------------+--------------------+----------------------------------+ | 2Ch | DCD | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 2Dh | DCD | Describes logical | 00h = DCD is active when read | | | ACTIVATION | level used | logic 0; DCD is not active when | | | | to control this | read logic 1 | | | | signal | 01h = DCD is active when read | | | | | logic 1; DCD is not active when | | | | | read logic 0 | +--------+------------+--------------------+----------------------------------+ | 2Eh | DSR | CIO port number | 00h-16h = CIO port number | | | PORT_NO | | FEh = From CC | | | | | FFh = DSR not | +--------+------------+--------------------+----------------------------------+ | 2Fh | DSR | Register bit | | | | BIT_NO | position for | | | | | this signal | | +--------+------------+--------------------+----------------------------------+ | 30h | DSR | Describes logical | 00h = DSR is active when read | | | ACTIVATION | level used | logic 0; DSR is not active when | | | | to control this | read logic 1 | | | | signal | 01h = DSR is active when read | | | | | logic 1; DSR is not active when | | | | | read logic 0 | +--------+------------+--------------------+----------------------------------+ | 31h | INDICATE | CIO port number | 00h-16h = CIO port number for ROS| | | PORT_NO | | and diagnostics | | | | | FFh = DSR not supported | +--------+------------+--------------------+----------------------------------+ | 33h | INDICATE | Describes logical | 00h = INDICATE is active when | | | ACTIVATION | level used | read logic 0; INDICATE is not | | | | to control this | active when read logic 1 | | | | signal | 01h = INDICATE is active when | | | | | read logic 1; INDICATE is not | | | | | active when read logic 0 | +--------+------------+--------------------+----------------------------------+ | 34h-3Ch| WRAP PLUG N| This 9-byte field describes how the control | | | INFORMATION| signals are wrapped | | | | | | | | ----+ | +--------|------------|-------------------- | | | | | Wrap for RxD | | +--------|------------|-------------------- | | | | | Wrap for CTS | 00h = Signal not wrapped | +--------|------------|-------------------- | | | | | Wrap for DSR | 01h = Signal wrapped to TxD | +--------|------------|-------------------- | | | | | Wrap for DCD | 02h = Signal wrapped to RTS | +--------|------------|-------------------- | | | | | Wrap for HRS(IN) > 03h = Signal wrapped to DTR | +--------|------------|-------------------- | | | | | Wrap for TXCIN | 04h = Signal wrapped to HRS(OUT)| +--------|------------|-------------------- | | | | | Wrap for RXCIN | 05h = Signal wrapped to TXCOUT | +--------|------------|-------------------- | | | | | Wrap for RI | 06h = Signal wrapped to CONTROL | +--------|------------|-------------------- | | | | | Wrap for INDICATE | | +--------|------------|-------------------- | | | | | ----+ | +--------+------------+-------------------------------------------------------+
The signal descriptions of the three connector strips (K0, K1, and K2) are listed in the following tables.
Table 21. K0 Adapter Card/Interface Board Connector Descriptions
+------------+--------------+----------+ | Connector | Signal | Signal | | Pin | Name | Source | | | | | +------------+--------------+----------+ | K0-01 | -TXREQ4 | DUSCC2 | +------------+--------------+----------+ | K0-02 | -RXREQ4 | DUSCC2 | +------------+--------------+----------+ | K0-03 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-04 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-05 | -TXREQ5 | DUSCC2 | +------------+--------------+----------+ | K0-06 | -RXREQ5 | DUSCC2 | +------------+--------------+----------+ | K0-07 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-08 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-09 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-10 | -TXREQ6 | DUSCC3 | +------------+--------------+----------+ | K0-11 | -RXREQ6 | DUSCC3 | +------------+--------------+----------+ | K0-12 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-13 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-14 | -TXREQ7 | DUSCC3 | +------------+--------------+----------+ | K0-15 | -RXREQ7 | DUSCC3 | +------------+--------------+----------+ | K0-16 | MEMCS | Adapter | +------------+--------------+----------+ | K0-17 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-18 | No | -------- | | | connection | ---- | +------------+--------------+----------+ | K0-19 | -RD | 80C186 | +------------+--------------+----------+ | K0-20 | -WR | 80C186 | +------------+--------------+----------+ | K0-21 | AD8 | 80C186 | +------------+--------------+----------+ | K0-22 | AD9 | 80C186 | +------------+--------------+----------+ | K0-23 | AD10 | 80C186 | +------------+--------------+----------+ | K0-24 | -DUSCC EOP | DUSCC | +------------+--------------+----------+ | K0-25 | AD11 | 80C186 | +------------+--------------+----------+ | K0-26 | AD12 | 80C186 | +------------+--------------+----------+ | K0-27 | AD13 | 80C186 | +------------+--------------+----------+ | K0-28 | AD14 | 80C186 | +------------+--------------+----------+ | K0-29 | AD15 | 80C186 | +------------+--------------+----------+ | K0-30 | -BHE | 80C186 | +------------+--------------+----------+
Table 22. K1 Adapter Card/Interface Board Connector Descriptions
+------------+--------------+----------+ | Connector | Signal | Signal | | Pin | Name | Source | | | | | +------------+--------------+----------+ | K1-01 | AD0 | 80C186 | +------------+--------------+----------+ | K1-02 | -12V | ----- | +------------+--------------+----------+ | K1-03 | AD1 | 80C186 | +------------+--------------+----------+ | K1-04 | AD2 | 80C186 | +------------+--------------+----------+ | K1-05 | AD3 | 80C186 | +------------+--------------+----------+ | K1-06 | AD4 | 80C186 | +------------+--------------+----------+ | K1-07 | AD5 | 80C186 | +------------+--------------+----------+ | K1-08 | AD6 | 80C186 | +------------+--------------+----------+ | K1-09 | +12V | ----- | +------------+--------------+----------+ | K1-10 | AD7 | 80C186 | +------------+--------------+----------+ | K1-11 | SCC2CS | DMAPIC | +------------+--------------+----------+ | K1-12 | SCC3CS | DMAPIC | +------------+--------------+----------+ | K1-13 | TXD0 | DUSCC0 | +------------+--------------+----------+ | K1-14 | RXD0 | DUSCC0 | +------------+--------------+----------+ | K1-15 | -RTS0 | DUSCC0 | +------------+--------------+----------+ | K1-16 | -12V | ----- | +------------+--------------+----------+ | K1-17 | -CTS0 | DUSCC0 | +------------+--------------+----------+ | K1-18 | -DCD0 | DUSCC0 | +------------+--------------+----------+ | K1-19 | RXCLK0 | DUSCC0 | +------------+--------------+----------+ | K1-20 | TXCLK0 | DUSCC0 | +------------+--------------+----------+ | K1-21 | TXD1 | DUSCC0 | +------------+--------------+----------+ | K1-22 | RXD1 | DUSCC0 | +------------+--------------+----------+ | K1-23 | +12V | DUSCC0 | +------------+--------------+----------+ | K1-24 | -RTS1 | DUSCC0 | +------------+--------------+----------+ | K1-25 | -CTS1 | DUSCC0 | +------------+--------------+----------+ | K1-26 | -DCD1 | DUSCC0 | +------------+--------------+----------+ | K1-27 | RXCLK1 | DUSCC0 | +------------+--------------+----------+ | K1-28 | TXCLK1 | DUSCC0 | +------------+--------------+----------+ | K1-29 | TXD2 | DUSCC1 | +------------+--------------+----------+ | K1-30 | RXD2 | DUSCC1 | +------------+--------------+----------+ | K1-31 | -RTS2 | DUSCC1 | +------------+--------------+----------+ | K1-32 | -CTS2 | DUSCC1 | +------------+--------------+----------+ | K1-33 | -DCD2 | DUSCC1 | +------------+--------------+----------+ | K1-34 | -RXCLK2 | DUSCC1 | +------------+--------------+----------+ | K1-35 | -TXCLK2 | DUSCC1 | +------------+--------------+----------+ | K1-36 | PA10 (-DTR1) | CIO0 | +------------+--------------+----------+ | K1-37 | TXD3 | DUSCC1 | +------------+--------------+----------+ | K1-38 | RXD3 | DUSCC1 | +------------+--------------+----------+ | K1-39 | -RTS3 | DUSCC1 | +------------+--------------+----------+ | K1-40 | -CTS3 | DUSCC1 | +------------+--------------+----------+ | K1-41 | -DCD3 | DUSCC1 | +------------+--------------+----------+ | K1-42 | -RXCLK3 | DUSCC1 | +------------+--------------+----------+ | K1-44 | PA30 (-DTR3) | CIO0 | +------------+--------------+----------+ | K1-45 | PA01 (-RI0) | CIO1 | +------------+--------------+----------+ | K1-46 | PA11 (-RI1) | CIO1 | +------------+--------------+----------+ | K1-47 | PA21 (-RI2) | CIO1 | +------------+--------------+----------+ | K1-48 | PA31 (-RI3) | CIO1 | +------------+--------------+----------+ | K1-49 | PA41 (-RI4) | CIO1 | +------------+--------------+----------+ | K1-50 | PA51 (-RI5) | CIO1 | +------------+--------------+----------+ | K1-51 | PA61 (-RI6) | CIO1 | +------------+--------------+----------+ | K1-52 | PA71 (-R17) | CIO1 | +------------+--------------+----------+ | K1-53 | PB01 (-HRS0) | CIO1 | +------------+--------------+----------+ | K1-54 | PB11 (-HRS1) | CIO1 | +------------+--------------+----------+ | K1-55 | PB21 (-HRS2) | CIO1 | +------------+--------------+----------+ | K1-56 | PB31 (-HRS3) | CIO1 | +------------+--------------+----------+ | K1-57 | PB41 (-HRS4) | CIO1 | +------------+--------------+----------+ | K1-58 | PB51 (-HRS5) | CIO1 | +------------+--------------+----------+ | K1-59 | PB61 (-HRS6) | CIO1 | +------------+--------------+----------+ | K1-60 | PB71 (-HRS7) | CIO1 | +------------+--------------+----------+
Table 23. K2 Adapter Card/Interface Board Connector Descriptions
+------------+--------------+--------------+ | Connector | Signal | Signal | | Pin | Name | Source | | | | | +------------+--------------+--------------+ | K2-01 | RDID86 | DMAPIC | +------------+--------------+--------------+ | K2-02 | -SCC3INT | DUSCC3 | +------------+--------------+--------------+ | K2-03 | GND | ----- | +------------+--------------+--------------+ | K2-04 | -SRDY | 80C186 | +------------+--------------+--------------+ | K2-05 | +DCE/-DTE 0 | ENREG (Note) | +------------+--------------+--------------+ | K2-06 | +5V | ----- | +------------+--------------+--------------+ | K2-07 | PA00 (-DTR0) | CIO0 | +------------+--------------+--------------+ | K2-08 | SCC3INTAK | DMAPIC | +------------+--------------+--------------+ | K2-09 | GND | ----- | +------------+--------------+--------------+ | K2-10 | PA20 (-DTR2) | CIO0 | +------------+--------------+--------------+ | K2-11 | -ROS CS | DMAPIC | +------------+--------------+--------------+ | K2-12 | +5V | ----- | +------------+--------------+--------------+ | K2-13 | PA40 (-DTR4) | CIO0 | +------------+--------------+--------------+ | K2-14 | PA50 (-DTR5) | CIO0 | +------------+--------------+--------------+ | K2-15 | GND | ----- | +------------+--------------+--------------+ | K2-16 | PA60 (-DTR6) | CIO0 | +------------+--------------+--------------+ | K2-17 | PA70 (-DTR7) | CIO0 | +------------+--------------+--------------+ | K2-18 | +5V | ----- | +------------+--------------+--------------+ | K2-19 | PB00 (-DSR0) | CIO0 | +------------+--------------+--------------+ | K2-20 | -DB IOCS | DMAPIC | +------------+--------------+--------------+ | K2-21 | GND | ----- | +------------+--------------+--------------+ | K2-22 | PB20 (-DSR2) | CIO0 | +------------+--------------+--------------+ | K2-23 | -RESET | 80C186 | +------------+--------------+--------------+ | K2-24 | +5V | ----- | +------------+--------------+--------------+ | K2-25 | PB40 (-DSR4) | CIO0 | +------------+--------------+--------------+ | K2-26 | PB50 (-DSR5) | CIO0 | +------------+--------------+--------------+ | K2-27 | GND | ----- | +------------+--------------+--------------+ | K2-28 | PB60 (-DSR6) | CIO0 | +------------+--------------+--------------+ | K2-29 | PB70 (-DSR7) | CIO0 | +------------+--------------+--------------+ | K2-30 | +5V | ----- | +------------+--------------+--------------+ | K2-31 | -DUSCC RD | DMAPIC | +------------+--------------+--------------+ | K2-32 | 7.4 MHz OSC | Adapter | +------------+--------------+--------------+ | K2-33 | +DCE/-DTE 1 | ENREG (Note) | +------------+--------------+--------------+ | K2-34 | -SCC2INT | DUSCC2 | +------------+--------------+--------------+ | K2-35 | -SCC2INTAK | DMAPIC | +------------+--------------+--------------+ | K2-36 | GND | ----- | +------------+--------------+--------------+ | K2-37 | ZR/-W | DMAPIC | +------------+--------------+--------------+ | K2-38 | -DUSCC WR | DMAPIC | +------------+--------------+--------------+ | K2-39 | 14.7 MHz OSC | Adapter | +------------+--------------+--------------+ | K2-40 | ZIEOF | Adapter | +------------+--------------+--------------+ | K2-41 | -ZAS | Adapter | +------------+--------------+--------------+ | K2-42 | GND | ----- | +------------+--------------+--------------+ | K2-43 | -ZDS | DMAPIC | +------------+--------------+--------------+ | K2-44 | +DCE/-DTE 2 | ENREG (Note) | +------------+--------------+--------------+ | K2-45 | +DCE/-DTE 3 | ENREG (Note) | +------------+--------------+--------------+ | K2-46 | PB01 (-DSR1) | CIO0 | +------------+--------------+--------------+ | K2-47 | PB03 (-DSR3) | CIO0 | +------------+--------------+--------------+ | K2-48 | GND | ----- | +------------+--------------+--------------+ | K2-49 | PC01 | CIO1 | +------------+--------------+--------------+ | K2-50 | PC11 | CIO1 | +------------+--------------+--------------+ | K2-51 | +DCE/-DTE 4 | ENREG (Note) | +------------+--------------+--------------+ | K2-52 | +DCE/-DTE 5 | ENREG (Note) | +------------+--------------+--------------+ | K2-53 | ALE | 80C186 | +------------+--------------+--------------+ | K2-54 | GND | ----- | +------------+--------------+--------------+ | K2-55 | 12.5 MHz CLK | 80C186 | +------------+--------------+--------------+ | K2-56 | +DCE/-DTE 6 | ENREG (Note) | +------------+--------------+--------------+ | K2-57 | +DCE/-DTE 7 | ENREG (Note) | +------------+--------------+--------------+ | K2-58 | PC21 | CIO1 | +------------+--------------+--------------+ | K2-59 | PC31 | CIO1 | +------------+--------------+--------------+ | K2-60 | GND | ----- | +------------+--------------+--------------+Note:
Refer to the enables register (ENREG) on page reference #1 for signal source details.
A light-emitting diode (LED) indicator provides a visual status of the watchdog timer status and error status. The LED turns on when the watchdog timer expires or a hardware error is detected by microcode on the co-processor adapter. The LED also turns on when power is initially applied to the co-processor adapter; it turns off after a successful power-on self-test (POST).
The LED is located near the top of the co-processor adapter, and can be viewed easily with the system unit cover removed. Co-Processor Adapter Card Layout
+----- LED indicator
+--V--------------------------------++++---------------------------+
| o+-----+ +---------+ +------+|||| +--------+ |
| |PROM | | 80C186 | |DUSCC0||||| | DMAPI | +---------+ |
| | | | CPU | +------+|||| | Gate | | RCBM | |
| +-----+ | | +------+|||| | Array | | Gate | |
| +-----+ +---------+ |DUSCC1||||| +--------+ | Array | |
| |PROM | +----+ +------+|||| | | |
| | | |CIO0| +----+|||| +---------+ |
| +-----+ +----+ |CIO1||||| |
| +------------------------++----+|||| |
| | RAM | |||| |
| +------------------------+ |||| +-+
+---------------------------------+ |||| ++ ++ +----+ |
+-++++--++---++-------+ +-------+
Three multi-pin connectors ^
(K0, K1, and K2) -----+
The following states are indicated by the LED:
The mechanical and electrical interface between the system unit and the co-processor adapter consists of the I/O channel connectors on the system board in the system unit and the card edge connectors on the co-processor adapter. Co-Processor Adapter Card Layout
+----- LED indicator
+--V--------------------------------++++---------------------------+
| o+-----+ +---------+ +------+|||| +--------+ |
| |PROM | | 80C186 | |DUSCC0||||| | DMAPI | +---------+ |
| | | | CPU | +------+|||| | Gate | | RCBM | |
| +-----+ | | +------+|||| | Array | | Gate | |
| +-----+ +---------+ |DUSCC1||||| +--------+ | Array | |
| |PROM | +----+ +------+|||| | | |
| | | |CIO0| +----+|||| +---------+ |
| +-----+ +----+ |CIO1||||| |
| +------------------------++----+|||| |
| | RAM | |||| |
| +------------------------+ |||| +-+
+---------------------------------+ |||| ++ ++ +----+ |
+-++++--++---++-------+ +-------+
^ ^ |
Card edge connectors ---+----------+ |
|
|
|
|
I/O channel connector ------------------+ |
V V
+---------------------+
System board -----+ | |
+---------------------------V----+---------------------+-+
| |
The multi-pin D-shell connector on the rear edge of the interface boards provides the connection to all communication ports. Interface Board Layout
+---------------------------------------------------+
| +-------------------------------+ +--+--+-+
+-+----+ | | |..|..|.|
+-+ | | | |..|..|.|
| |Multi-| | | |..|..|.| Two 60-pin
| |pin | | SCCs, drivers, receivers, | |..|..|.| connectors
| |conn | | and discrete components | |..|..|.| (K1 and K2)
| |K9B | | | |..|..|.|<-------
| | | | | |..|..|.| One 30-pin
+-+ | | | |..|..|.| connector
+-+----+ +-------------------------------+ |..|..|.| (K0)
+-------------------------------------------+--+--+-+
K2 K1 K0
This chapter contains the following information for the Eight-Port RS-232 Interface Board/A and related external devices:
The eight-port RS-232 interface board/A contains the signal conditioning circuitry necessary to convert from TTL logic levels to RS-232-D logic levels and vice versa for eight serial RS-232-D ports. The signals exit the interface board through the 100-pin D-shell connector.
Clocking is supported for all eight ports of the eight-port RS-232 interface board.
This interface board has a data rate of up to 38.4k baud, full duplex, with all eight ports operating concurrently.
The voltage requirements for this board are +5V, +12V, and -12V.
The following tables provide complete signal relationships between the DUSCC, the CIO, the eight-port RS-232 interface board/A, serial ports, and cables. RS-232-D interchange circuit designations are also provided.
Note:
All SCC and CIO signal sources/pin numbers are logical signal sources and are not electrically connected to the 100-pin, D-shell connector pins.
+----------------------------------------------------+ | RS-232-D Port 0 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD0 |DUSCC-0 | 39/TXDA | 51 | 02/BA - 103 | | RXD0 |DUSCC-0 | 40/RXDA | 02 | 03/BB - 104 | | RTS0 |DUSCC-0 | 45/-RTSA | 01 | 04/CA - 105 | | CTS0 |DUSCC-0 | 35/-CTSA | 77 | 05/CB - 106 | | TXCLK0 |DUSCC-0 | 44/-TRXCA| 52 | 24/DA - 113 | | SG | --- | | 19 | 07/AB - 102 | | DCD0 |DUSCC-0 | 42/-DCDA | 28 | 08/CF - 109 | | RXCLK0 |DUSCC-0 | 43/RTXCA | 78 | 17/DD - 115 | | DTR0 | CIO-0 | 37/PA-00 | 76 | 20/CD - 108.2| | DSR0 | CIO-0 | 10/PB-00 | 53 | 06/CC - 107 | | HRS0 | CIO-1 | 10/PB-01 | 27 | 23/CI - 111 | | RI0 | CIO-1 | 37/PA-01 | 03 | 22/CE - 125 | | TXCLKIN0|DUSCC-0 | 44/-TRXCA| 29 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 1 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD1 |DUSCC-0 | 15/TXDB | 54 | 02/BA - 103 | | RXD1 |DUSCC-0 | 14/RXDB | 05 | 03/BB - 104 | | RTS1 |DUSCC-0 | 09/-RTSB | 04 | 04/CA - 105 | | CTS1 |DUSCC-0 | 19/-CTSB | 80 | 05/CB - 106 | | TXCLK1 |DUSCC-0 | 10/TRXCB | 55 | 24/DA - 113 | | SG | --- | | 19 | 07/AB - 102 | | DCD1 |DUSCC-0 | 12/-DCDB | 31 | 08/CF - 109 | | RXCLK1 |DUSCC-0 | 11/RTXCB | 81 | 17/DD - 115 | | DTR1 | CIO-0 | 36/PB-10 | 79 | 20/CD - 108.2| | DSR1 | CIO-0 | 11/PB-10 | 56 | 06/CC - 107 | | HRS1 | CIO-1 | 11/PB-11 | 30 | 23/CI - 111 | | RI1 | CIO-1 | 36/PA-11 | 06 | 22/CE - 125 | | TXCLKIN1|DUSCC-0 | 10/TRXCB | 32 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 2 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD2 |DUSCC-1 | 39/TXDA | 07 | 02/BA - 103 | | RXD2 |DUSCC-1 | 40/RXDA | 83 | 03/BB - 104 | | RTS2 |DUSCC-1 | 45/-RTSA | 82 | 04/CA - 105 | | CTS2 |DUSCC-1 | 35/-CTSA | 34 | 05/CB - 106 | | TXCLK2 |DUSCC-1 | 44/-TRXCA| 08 | 24/DA - 113 | | SG | --- | | 26 | 07/AB - 102 | | DCD2 |DUSCC-1 | 42/-DCDA | 59 | 08/CF - 109 | | RXCLK2 |DUSCC-1 | 43/RTXCA | 35 | 17/DD - 115 | | DTR2 | CIO-0 | 35/PA-20 | 33 | 20/CD - 108.2| | DSR2 | CIO-0 | 12/PB-20 | 09 | 06/CC - 107 | | HRS2 | CIO-1 | 12/PB-21 | 58 | 23/CI - 111 | | RI2 | CIO-1 | 35/PA-21 | 84 | 22/CE - 125 | | TXCLKIN2|DUSCC-1 | 44/-TRXCA| 60 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 3 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD3 |DUSCC-1 | 15/TXDB | 10 | 02/BA - 103 | | RXD3 |DUSCC-1 | 14/RXDB | 86 | 03/BB - 104 | | RTS3 |DUSCC-1 | 09/-RTSB | 85 | 04/CA - 105 | | CTS3 |DUSCC-1 | 19/-CTSB | 37 | 05/CB - 106 | | TXCLK3 |DUSCC-1 | 10/TRXCB | 11 | 24/DA - 113 | | SG | --- | | 26 | 07/AB - 102 | | DCD3 |DUSCC-1 | 12/-DCDB | 62 | 08/CF - 109 | | RXCLK3 |DUSCC-1 | 11/RTXCB | 38 | 17/DD - 115 | | DTR3 | CIO-0 | 34/PB-30 | 36 | 20/CD - 108.2| | DSR3 | CIO-0 | 13/PB-30 | 12 | 06/CC - 107 | | HRS3 | CIO-1 | 13/PB-31 | 61 | 23/CI - 111 | | RI3 | CIO-1 | 34/PA-31 | 87 | 22/CE - 125 | | TXCLKIN3|DUSCC-1 | 10/TRXCB | 63 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 4 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD4 |DUSCC-2 | 39/TXDA | 13 | 02/BA - 103 | | RXD4 |DUSCC-2 | 40/RXDA | 89 | 03/BB - 104 | | RTS4 |DUSCC-2 | 45/-RTSA | 88 | 04/CA - 105 | | CTS4 |DUSCC-2 | 35/-CTSA | 40 | 05/CB - 106 | | TXCLK4 |DUSCC-2 | 44/-TRXCA| 14 | 24/DA - 113 | | SG | --- | | 57 | 07/AB - 102 | | DCD4 |DUSCC-2 | 42/-DCDA | 65 | 08/CF - 109 | | RXCLK4 |DUSCC-2 | 43/RTXCA | 41 | 17/DD - 115 | | DTR4 | CIO-0 | 33/PA-40 | 39 | 20/CD - 108.2| | DSR4 | CIO-0 | 14/PB-40 | 15 | 06/CC - 107 | | HRS4 | CIO-1 | 14/PB-41 | 64 | 23/CI - 111 | | RI4 | CIO-1 | 33/PA-41 | 90 | 22/CE - 125 | | TXCLKIN4|DUSCC-2 | 44/-TRXCA| 66 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 5 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD5 |DUSCC-2 | 15/TXDB | 16 | 02/BA - 103 | | RXD5 |DUSCC-2 | 14/RXDB | 92 | 03/BB - 104 | | RTS5 |DUSCC-2 | 09/-RTSB | 91 | 04/CA - 105 | | CTS5 |DUSCC-2 | 19/-CTSB | 43 | 05/CB - 106 | | TXCLK5 |DUSCC-2 | 10/TRXCB | 17 | 24/DA - 113 | | SG | --- | | 57 | 07/AB - 102 | | DCD5 |DUSCC-2 | 12/-DCDB | 68 | 08/CF - 109 | | RXCLK5 |DUSCC-2 | 11/RTXCB | 44 | 17/DD - 115 | | DTR5 | CIO-0 | 32/PB-50 | 42 | 20/CD - 108.2| | DSR5 | CIO-0 | 15/PB-50 | 18 | 06/CC - 107 | | HRS5 | CIO-1 | 15/PB-51 | 67 | 23/CI - 111 | | RI5 | CIO-1 | 32/PA-51 | 93 | 22/CE - 125 | | TXCLKIN5|DUSCC-2 | 10/TRXCB | 69 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 6 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD6 |DUSCC-3 | 39/TXDA | 94 | 02/BA - 103 | | RXD6 |DUSCC-3 | 40/RXDA | 46 | 03/BB - 104 | | RTS6 |DUSCC-3 | 45/-RTSA | 45 | 04/CA - 105 | | CTS6 |DUSCC-3 | 35/-CTSA | 71 | 05/CB - 106 | | TXCLK6 |DUSCC-3 | 44/-TRXCA| 95 | 24/DA - 113 | | SG | --- | | 97 | 07/AB - 102 | | DCD6 |DUSCC-3 | 42/-DCDA | 21 | 08/CF - 109 | | RXCLK6 |DUSCC-3 | 43/RTXCA | 72 | 17/DD - 115 | | DTR6 | CIO-0 | 31/PA-60 | 70 | 20/CD - 108.2| | DSR6 | CIO-0 | 16/PB-60 | 96 | 06/CC - 107 | | HRS6 | CIO-1 | 16/PB-61 | 20 | 23/CI - 111 | | RI6 | CIO-1 | 31/PA-61 | 47 | 22/CE - 125 | | TXCLKIN6|DUSCC-3 | 44/-TRXCA| 22 | 15/DB - 114 | +---------+--------+----------+-------+--------------+ +----------------------------------------------------+ | RS-232-D Port 7 | +---------+--------+----------+-------+--------------+ | Signal | Signal |DUSCC/CIO | D-Conn| RS-232-D | | Name | Source | Pin/Name | Pin # | Pin/Name | +---------+--------+----------+-------+--------------+ | TXD7 |DUSCC-3 | 15/TXDB | 48 | 02/BA - 103 | | RXD7 |DUSCC-3 | 14/RXDB | 74 | 03/BB - 104 | | RTS7 |DUSCC-3 | 09/-RTSB | 73 | 04/CA - 105 | | CTS7 |DUSCC-3 | 19/-CTSB | 24 | 05/CB - 106 | | TXCLK7 |DUSCC-3 | 10/TRXCB | 49 | 24/DA - 113 | | SG | --- | | 97 | 07/AB - 102 | | DCD7 |DUSCC-3 | 12/-DCDB | 99 | 08/CF - 109 | | RXCLK7 |DUSCC-3 | 11/RTXCB | 25 | 17/DD - 115 | | DTR7 | CIO-0 | 30/PB-70 | 23 | 20/CD - 108.2| | DSR7 | CIO-0 | 17/PB-70 | 50 | 06/CC - 107 | | HRS7 | CIO-1 | 17/PB-71 | 98 | 23/CI - 111 | | RI7 | CIO-1 | 30/PA-71 | 75 | 22/CE - 125 | | TXCLKIN7|DUSCC-3 | 10/TRXCB | 100 | 15/DB - 114 | +---------+--------+----------+-------+--------------+
The following figure shows the pinout configuration of the 100-pin D-shell female connector (K9B) on the interface board.
26 \ / 01 51 \ / 27 75 \ / 52 100 \ / 76The RS-232-D pin assignments for the 100-pin connector on the eight-port RS-232 interface board/A are listed in the following table.
Table 24. Eight-Port RS-232-D Connector Pin Assignments
+--------+----+--------------------------+----------+ | Signal | | 100-Pin Connector | 25-Pin | | Name | I/O| (Ports 0-7) | Connector| | | | 0 1 2 3 4 5 6 7 | Pin/Name | +--------+----+--------------------------+----------+ | TXD | O | 51 54 07 10 13 16 94 48 | 02/BA | +--------+----+--------------------------+----------+ | RXD | I | 02 05 83 86 89 92 46 74 | 03/BB | +--------+----+--------------------------+----------+ | RTS | O | 01 04 82 85 88 91 45 73 | 04/CA | +--------+----+--------------------------+----------+ | CTS | I | 77 80 34 37 40 43 71 24 | 05/CB | +--------+----+--------------------------+----------+ | DCD | I | 28 31 59 62 65 68 21 99 | 08/CF | +--------+----+--------------------------+----------+ | DTR | O | 76 79 33 36 39 42 70 23 | 20/CD | +--------+----+--------------------------+----------+ | DSR | I | 53 56 09 12 15 18 96 50 | 06/CC | +--------+----+--------------------------+----------+ | HRS | I | 27 30 58 61 64 67 20 98 | 23/CI | +--------+----+--------------------------+----------+ | RI | I | 03 06 84 87 90 93 47 75 | 22/CE | +--------+----+--------------------------+----------+ | TXCLKIN| I | 29 32 60 63 66 69 22 100 | 15/DB | +--------+----+--------------------------+----------+ | TXCLK | O | 52 55 08 11 14 17 95 49 | 24/DA | +--------+----+--------------------------+----------+ | RXCLK | I | 78 81 35 38 41 44 72 25 | 17/DD | +--------+----+--------------------------+----------+ | SG | -- | 19 19 26 26 57 57 97 97 | 07/AB | +--------+----+--------------------------+----------+
An Eight-Port Cable is available as an option to support the Eight-Port RS-232 Interface Board/A. The Eight-port cable converts the 100-pin female D-shell connector (K9B) on the co-processor adapter to appropriate connector interfaces for external cabling. This cable is 1.2 meters (4 feet) long. It has a 100-pin male D-shell connector (K9A) on one end that attaches to the connector on the co-processor adapter. At other end of the cable is a molded distribution box, containing eight 25-pin male D-shell connectors (K00 - K07) that attach to external cabling.
The approximate dimensions of the distribution box are 203 mm (8 in.) long by 76 mm (3 in.) wide, by 38 mm (1.5 in.) deep.
Eight-Port Cable
+-----+ +-----+ +------------------+
| +-+ +-+ | | Port 0 (K00) |
| | | | | +------------+ |
|100-pin| |100-pin+-----------------------------+ \------------/ |
|female | | male +-----------------------------+ Port 1 (K01) |
| (K9B) | | (K9A) | Cable (1.2 m) | +------------+ |
| | | | | \------------/ |
| +-+ +-+ | | Port 2 (K02) |
+-----+ +-----+ | +------------+ |
Rear of | \------------/ |
Co-Processor | Port 3 (K03) |
Adapter | +------------+ |
| \------------/ |
| Port 4 (K04) |
| +------------+ |
| \------------/ |
| Port 5 (K05) |
+---------------------------+ | +------------+ |
1 \ . . . . . . . . . . . . . / 13 | \------------/ |
14 \ . . . . . . . . . . . . / 25 | Port 6 (K06) |
+-----------------------+ | +------------+ |
25-Pin D-Shell Connectors ---------->| \------------/ |
(K00 - K07) | Port 7 (K07) |
| +------------+ |
| \------------/ |
| |
+------------------+
The following table shows the connections from connector K9A to connectors K00 through K07.
+---------------------------------------------------------------+ | K9A to K00 through K07 Connections | +-----------++-----------++-----------++-----------++-----------+ |K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # | +-----------++-----------++-----------++-----------++-----------+ |01 K00-04||21 K06-08||41 K04-17||61 K03-23||81 K01-17| |02 K00-03||22 K06-15||42 K05-20||62 K03-08||82 K02-04| |03 K00-22||23 K07-20||43 K05-05||63 K03-15||83 K02-03| |04 K01-04||24 K07-05||44 K05-17||64 K04-23||84 K02-22| |05 K01-03||25 K07-17||45 K06-04||65 K04-08||85 K03-04| |06 K01-22||26 Gnd 2&3||46 K06-03||66 K04-15||86 K03-03| |07 K02-02||27 K00-23||47 K06-22||67 K05-23||87 K03-22| |08 K02-24||28 K01-08||48 K07-02||68 K05-08||88 K04-04| |09 K02-06||29 K00-15||49 K07-24||69 K05-15||89 K04-03| |10 K03-02||30 K01-23||50 K07-06||70 K06-20||90 K04-22| |11 K03-24||31 K01-08||51 K00-02||71 K06-05||91 K05-04| |12 K03-06||32 K01-15||52 K00-24||72 K06-17||92 K05-03| |13 K04-02||33 K02-20||53 K00-06||73 K07-04||93 K05-22| |14 K04-24||34 K02-05||54 K01-02||74 K07-03||94 K06-02| |15 K04-06||35 K02-17||55 K01-24||75 K07-22||95 K06-24| |16 K05-02||36 K03-20||56 K01-06||76 K00-20||96 K06-06| |17 K05-24||37 K03-05||57 Gnd 4&5||77 K00-05||97 Gnd 6&7| |18 K05-06||38 K03-17||58 K02-23||78 K00-17||98 K07-23| |19 Gnd 0&1||39 K04-20||59 K02-08||79 K01-20||99 K07-08| |20 K06-23||40 K04-05||60 K02-15||80 K01-05||100 K07-15| +-----------++-----------++-----------++-----------++-----------+
An optional diagnostic wrap plug is available with the Hardware Maintenance Library for diagnosing problems with the eight-port RS-232 interface board/A, as well as the co-processor adapter. This 100-pin male wrap plug (P/N 15F8848) is designed to wrap all signals used for RS-232-D operation at connector K9B. (No cable is associated with this wrap plug.)
The following table shows all wrapped signal connections.
+----+-------------------+----------------------------------+ | | Connector | RS-232-D | |Port| K9B Pins | Signals Wrapped | +----+-------------------+----------------------------------+ | | 51 - 02 | TXD0 -> RXD0 | | | 01 - 77 - 28 - 29 | RTS0 -> CTS0 -> DCD0 -> TXCLKIN0 | | 0 | 52 - 78 | TXCLK0 -> RXCLK0 | | | 76 - 53 - 03 - 27 | DTR0 -> DSR0 -> RI0 -> HRS0 | +----+-------------------+----------------------------------+ | | 54 - 05 | TXD1 -> RXD1 | | | 04 - 80 - 31 - 32 | RTS1 -> CTS1 -> DCD1 -> TXCLKIN1 | | 1 | 55 - 81 | TXCLK1 -> RXCLK1 | | | 79 - 56 - 06 - 30 | DTR1 -> DSR1 -> RI1 -> HRS1 | +----+-------------------+----------------------------------+ | | 07 - 83 | TXD2 -> RXD2 | | | 82 - 34 - 59 - 60 | RTS2 -> CTS2 -> DCD2 -> TXCLKIN2 | | 2 | 08 - 35 | TXCLK2 -> RXCLK2 | | | 33 - 09 - 84 - 58 | DTR2 -> DSR2 -> RI2 -> HRS2 | +----+-------------------+----------------------------------+ | | 10 - 86 | TXD3 -> RXD3 | | | 85 - 37 - 62 - 63 | RTS3 -> CTS3 -> DCD3 -> TXCLKIN3 | | 3 | 11 - 38 | TXCLK3 -> RXCLK3 | | | 36 - 12 - 87 - 61 | DTR3 -> DSR3 -> RI3 -> HRS3 | +----+-------------------+----------------------------------+ | | 13 - 89 | TXD4 -> RXD4 | | | 88 - 40 - 65 - 66 | RTD4 -> CTS4 -> DCD4 -> TXCLKIN4 | | 4 | 14 - 41 | TXCLK4 -> RXCLK4 | | | 39 - 15 - 90 - 64 | DTR4 -> DSR4 -> RI4 -> HRS4 | +----+-------------------+----------------------------------+ | | 16 - 92 | TXD5 -> RXD5 | | | 91 - 43 - 68 - 69 | RTS5 -> CTS5 -> DCD5 -> TXCLKIN5 | | 5 | 17 - 44 | TXCLK5 -> RXCLK5 | | | 42 - 18 - 93 - 67 | DTR5 -> DSR5 -> RI5 -> HRS5 | +----+-------------------+----------------------------------+ | | 94 - 46 | TXD6 -> RXD6 | | | 45 - 71 - 21 - 22 | RTS6 -> CTS6 -> DCD6 -> TXCLKIN6 | | 6 | 95 - 72 | TXCLK6 -> RXCLK6 | | | 70 - 96 - 47 - 20 | DTR6 -> DSR6 -> RI6 -> HRS6 | +----+-------------------+----------------------------------+ | | 48 - 74 | TXD7 -> RXD7 | | | 73 - 24 - 99 - 100| RTS7 -> CTS7 -> DCD7 -> TXCLKIN7 | | 7 | 49 - 25 | TXCLK7 -> RXCLK7 | | | 23 - 50 - 75 - 98 | DTR7 -> DSR7 -> RI7 -> HRS7 | +----+-------------------+----------------------------------+
An optional diagnostic wrap plug for the eight-port cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the interface cable. This 25-pin female wrap plug (P/N 33F8985) is used for RS-232-D operation on ports 0 through 7.
The signals that are wrapped within the wrap plug are shown below. The wrap connection is made from each transmit output signal and looped back to the corresponding receive input signal on the 25-pin D-shell connector.
+----------------------------------------------------+ | Wrap Connections for Ports 0 through 7 | +--------------------+-------------------------------+ | Associated Pins | RS-232-D Signals Wrapped | +--------------------+-------------------------------+ | 02 - 03 | TXD -> RXD | | 04 - 05 - 08 - 15 | RTS -> CTS -> DCD -> TXCLKIN | | 24 - 17 | TXCLK -> RXCLK | | 20 - 06 - 22 - 23 | DTR -> DSR -> RI -> HRS | +--------------------+-------------------------------+
This chapter contains the following information for the Eight-Port RS-422-A Interface Board/A and related external devices:
The Eight-Port RS-422-A Interface Board/A contains the signal conditioning circuitry that converts TTL logic levels to the required logic levels (and vice versa) for eight serial RS-422-A ports, or six serial RS-422 ports and two serial X.21 ports. RS-422-A is supported on ports 0 through 7; X.21 is supported only on ports 0 and 1. Protocols for these electrical signals are user-programmable. The signals exit the interface board through the 100-pin D-shell connector.
Inbound transmit and receive clocking is supported for all eight ports of the eight-port RS-422 interface board.
The DTE/DCE clock select line is described under "Enables Register (ENREG)". This line is used as follows:
This interface board has a data rate of up to 64K baud, duplex, with all eight RS-422-A ports operating concurrently. Any single RS-422-A port can have a data rate of up to 2.048M baud(3), duplex.
The board supports up to two X.21 ports (0 and 1), running concurrently at 64K baud.
The ID for this interface board is 21h.
The voltage requirements for this board are +5V.
The maximum cable length of the interface cable is approximately 122 meters (400 feet). Cables are not supported for outdoor operation.
For outdoor applications or installations requiring more than 122 meters (400 feet), contact your IBM Representative.
A surge protection adapter can be used to provide voltage suppression circuitry for each port. See "Surge Protection Adapter".
The interface board ROS for the co-processor adapter is described fully in Chapter 3. "Electrical Interfaces". These tables also apply to the RS-422 interface board.
The eight-port RS-422 interface board supports
X.21 operation on ports 0 and 1. The
ROS field names for the X.21 signals are listed in Figure 29.,
along with the field names for the corresponding RS-232/RS-422 signals.
Figure 29. ROS Field Names
+---------------+-----------------+ | X.21 | RS-232/RS-422 | +---------------+-----------------+ | CONTROL | RTS | | INDICATE | CTS | | TX_EN | TXBLK | | X21_EN | DTR | | X21S0 | DSR | | X21S1 | DCD | +---------------+-----------------+
Ports 0 and 1 have the following added features:
Interface Signal X.21 Name ------ --------- TxD T (transmit) RxD R (receive) -RTS C (control) -CTS I (indication) RxCLK S (signal element timing)
Ports 0 & 1 Realtime Control Microcode X.21 Name Logical Control Line Services Name ---------- ---------------------------------- -TxEN TXBLK -X21EN DTR -X21S1 DCD -X21S0 DSR
+-------+-------+---------------------------------------------+ |-X21S1 |-X21S0 | Status | +-------+-------+---------------------------------------------+ | 0 | 0 | At least 16 bits of 0s were detected, | | | | (I=off,-X21EN=true). | | 1 | 1 | At least 16 bits of 1s were detected, | | | | (I=off,-X21EN=true). | | 1 | 0 | At least 16 bits of alternating 0s and 1s | | | | (that is, 010101..) were detected, | | | | (I=off, -X21EN=true). | | 0 | 1 | Reset state (-X21EN=false). | +-------+-------+---------------------------------------------+
For proper operation, the pattern recognition hardware should be reset prior to any communications. The sample code shown in Figure 31. accomplishes this reset. This code assumes -X21EN is in the disabled state. A pull-up resistor assures the disabled state, until the CIO bits are enabled. This routine resets the hardware, even if there is no external clock.
The code functions as follows:
;------ DUSCC EQUATES FOR PROM SERVICES CALL
CTPRH EQU 08H ;COUNTER PRESET HIGH REGISTER
CTPRL EQU 09H ;COUNTER PRESET LOW REGISTER
CTCR EQU 0AH ;COUNTER CONTROL REGISTER
PCR EQU 0EH ;PIN CONFIGURATION REGISTER
CCR EQU 0FH ;CHANNEL COMMAND REGISTER
;------ DUSCC INIT TABLE FOR X.21 RESET
X21_RST_TBL DB 8 ;8 REGS TO WRITE
DB PCR,23H ;RTXC=IN , TRXC=COUNTER OUTPUT
DB CTPRH,00H ;PRESET HIGH
DB CTPRL,02H ;PRESET LOW
DB CTCR,22H ;PULSE OUTPUT, CLOCK SOURCE = X1/CLK
DB CCR,83H ;LOAD PRESET VALUE TO COUNTER
DB CCR,80H ;START COUNTER TO RESET X.21 PAL
DB CCR,81H ;STOP COUNTER
DB PCR,20H ;PUT RTXC AND TRXC BACK TO INPUT MODE
;------ CODE START HERE
;------ INIT X.21 PORT 0
MOV DX,800H ;
IN AL,DX ;
AND AL,11111110B ;SELECT DTE CLOCK FOR PORT 0
OUT DX,AL ;
LEA SI,X21_RST_TBL ;GET TABLE POINTER
MOV AX,0 ;AH=0, AL=PORT#. PREPARE TO INIT PORT 0
INT 0A4H ;CALL PROM SERVICES TO INIT DUSCC FROM TABLE
MOV DX,800H ;
IN AL,DX ;
OR AL,00000001B ;SELECT DCE CLOCK FOR PORT 0
OUT DX,AL ;
;------ INIT X.21 PORT 1
MOV DX,800H ;
IN AL,DX ;
AND AL,11111101B ;SELECT DTE CLOCK FOR PORT 1
OUT DX,AL ;
LEA SI,X21_RST_TBL ;GET TABLE POINTER
MOV AX,1 ;AH=0, AL=PORT#. PREPARE TO INIT PORT 1
INT 0A4H ;CALL PROM SERVICES TO INIT DUSCC FROM TABLE
MOV DX,800H ;
IN AL,DX ;
OR AL,00000010B ;SELECT DCE CLOCK FOR PORT 1
OUT DX,AL ;
The following tables provide the signal relationships between the DUSCC, the CIO, the eight-port RS-422 interface board, and the serial ports. Input and output direction is given relative to the DUSCC and CIO.
+---------------------------------------------------------+ | Port 0, RS-422 & X.21 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD0 | DUSCC-0 | 39/TXDA | 51 | 02/SDA0 | O | | | | | 52 | 24/SDB0 | O | | RxD0 | DUSCC-0 | 40/RXDA | 02 | 03/RDA0 | I | | | | | 78 | 17/RDB0 | I | | -RTS0 | DUSCC-0 | 45/RTSAN | 01 | 04/RSA0 | O | | | | | 76 | 20/RSB0 | O | | -CTS0 | DUSCC-0 | 35/CTSAN | 77 | 05/CSA0 | I | | | | | 53 | 06/CSB0 | I | | TxCLK0 | DUSCC-0 | 44/TRXCA | 28 | 08/STA0 ** | I | | | | | 03 | 22/STB0 ** | I | | RxCLK0 | DUSCC-0 | 43/RTXCA | 29 | 15/RTA0 ** | I | | | | | 27 | 23/RTB0 ** | I | | SG | --- | --- | 19 | 07/SG | - | | -TxEN0 | CIO-0 | 37/PA0 | | | O | | -X21EN0 | CIO-0 | 35/PA2 | | | O | | -X21S1P0| CIO-0 | 11/PB1 | | | I | | -X21S0P0| CIO-0 | 10/PB0 | | | I | +---------+---------+----------+-------+------------+-----+* RS-449 signal naming conventions are used. IBM makes no claims as to compatibility with RS-449.
** These signal pairs are terminated from line-to-line by a 120-ohm resistor.
+---------------------------------------------------------+ | Port 1, RS-422 & X.21 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD1 | DUSCC-0 | 15/TXDB | 54 | 02/SDA1 | O | | | | | 55 | 24/SDB1 | O | | RxD1 | DUSCC-0 | 14/RXDB | 05 | 03/RDA1 | I | | | | | 81 | 17/RDB1 | I | | -RTS1 | DUSCC-0 | 09/RTSBN | 04 | 04/RSA1 | O | | | | | 79 | 20/RSB1 | O | | -CTS1 | DUSCC-0 | 19/CTSBN | 80 | 05/CSA1 | I | | | | | 56 | 06/CSB1 | I | | TxCLK1 | DUSCC-0 | 10/TRXCB | 31 | 08/STA1 ** | I | | | | | 06 | 22/STB1 ** | I | | RxCLK1 | DUSCC-0 | 11/RTXCB | 32 | 15/RTA1 ** | I | | | | | 30 | 23/RTB1 ** | I | | SG | --- | --- | 19 | 07/SG | - | | -TxEN1 | CIO-0 | 36/PA1 | | | O | | -X21EN1 | CIO-0 | 34/PA3 | | | O | | -X21S1P1| CIO-1 | 36/PA1 | | | I | | -X21S0P1| CIO-1 | 37/PA0 | | | I | +---------+---------+----------+-------+------------+-----+* RS-449 signal naming conventions are used. IBM makes no claims as to compatibility with RS-449.
** These signal pairs are terminated from line-to-line by a 120-ohm resistor.
+---------------------------------------------------------+ | Port 2, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD2 | DUSCC-1 | 39/TXD2 | 07 | 02/SDA2 | O | | | | | 08 | 24/SDB2 | O | | RxD2 | DUSCC-1 | 40/RXDA | 83 | 03/RDA2 | I | | | | | 35 | 17/RDB2 | I | |-RTS2 | DUSCC-1 | 45/-RTSAN| 82 | 04/RSA2 | O | | | | | 33 | 20/RSB2 | O | |-CTS2 | DUSCC-1 | 35/-CTSAN| 34 | 05/CSA2 | I | | | | | 09 | 06/CSB2 | I | | TxCLK2 | DUSCC-1 | 44/TRXCA | 59 | 08/STA2 ** | I | | | | | 84 | 22/STB2 ** | I | | RxCLK2 | DUSCC-1 | 43/RTXCA | 60 | 15/RTA2 ** | I | | | | | 58 | 23/RTB2 ** | I | | SG | --- | --- | 26 | 07/SG | - | +---------+---------+----------+-------+------------+-----+ +---------------------------------------------------------+ | Port 3, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD3 | DUSCC-1 | 15/TXDB | 10 | 02/SDA3 | O | | | | | 11 | 24/SDB3 | O | | RxD3 | DUSCC-1 | 14/RXDB | 86 | 03/RDA3 | I | | | | | 38 | 17/RDB3 | I | |-RTS3 | DUSCC-1 | 09/-RTSBN| 85 | 04/RSA3 | O | | | | | 36 | 20/RSB3 | O | |-CTS3 | DUSCC-1 | 19/-CTSBN| 37 | 05/CSA3 | I | | | | | 12 | 06/CSB3 | I | | TxCLK3 | DUSCC-1 | 10/TRXCB | 62 | 08/STA3 ** | I | | | | | 87 | 22/STB3 ** | I | | RxCLK3 | DUSCC-1 | 11/RTXCB | 63 | 15/RTA3 ** | I | | | | | 61 | 23/RTB3 ** | I | | SG | --- | --- | 26 | 07/SG | - | +---------+---------+----------+-------+------------+-----+* RS-449 signal naming conventions are used. IBM makes no claims as to compatibility with RS-449.
** These signal pairs are terminated from line-to-line by a 120-ohm resistor.
+---------------------------------------------------------+ | Port 4, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD4 | DUSCC-2 | 39/TXDA | 13 | 02/SDA3 | O | | | | | 14 | 24/SDB3 | O | | RxD4 | DUSCC-2 | 40/RXDA | 89 | 03/RDA3 | I | | | | | 41 | 17/RDB3 | I | |-RTS4 | DUSCC-2 | 45/-RTSAN| 88 | 04/RSA3 | O | | | | | 39 | 20/RSB3 | O | |-CTS4 | DUSCC-2 | 35/-CTSAN| 40 | 05/CSA3 | I | | | | | 15 | 06/CSB3 | I | | TxCLK4 | DUSCC-2 | 44/TRXCA | 65 | 08/STA3 ** | I | | | | | 90 | 22/STB3 ** | I | | RxCLK4 | DUSCC-2 | 43/RTXCA | 66 | 15/RTA3 ** | I | | | | | 64 | 23/RTB3 ** | I | | SG | --- | --- | 57 | 07/SG | - | +---------+---------+----------+-------+------------+-----+ +---------------------------------------------------------+ | Port 5, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD5 | DUSCC-2 | 15/TXDB | 16 | 02/SDA3 | O | | | | | 17 | 24/SDB3 | O | | RxD5 | DUSCC-2 | 14/RXDB | 92 | 03/RDA3 | I | | | | | 44 | 17/RDB3 | I | |-RTS5 | DUSCC-2 | 09/-RTSBN| 91 | 04/RSA3 | O | | | | | 42 | 20/RSB3 | O | |-CTS5 | DUSCC-2 | 19/-CTSBN| 43 | 05/CSA3 | I | | | | | 18 | 06/CSB3 | I | | TxCLK5 | DUSCC-2 | 10/TRXCB | 68 | 08/STA3 ** | I | | | | | 93 | 22/STB3 ** | I | | RxCLK5 | DUSCC-2 | 11/RTXCB | 69 | 15/RTA3 ** | I | | | | | 67 | 23/RTB3 ** | I | | SG | --- | --- | 57 | 07/SG | - | +---------+---------+----------+-------+------------+-----+* RS-449 signal naming conventions are used. IBM makes no claims as to compatibility with RS-449.
** These signal pairs are terminated from line-to-line by a 120-ohm resistor.
+---------------------------------------------------------+ | Port 6, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD6 | DUSCC-3 | 39/TXDA | 94 | 02/SDA3 | O | | | | | 95 | 24/SDB3 | O | | RxD6 | DUSCC-3 | 40/RXDA | 46 | 03/RDA3 | I | | | | | 72 | 17/RDB3 | I | |-RTS6 | DUSCC-3 | 45/-RTSAN| 45 | 04/RSA3 | O | | | | | 70 | 20/RSB3 | O | |-CTS6 | DUSCC-3 | 35/-CTSAN| 71 | 05/CSA3 | I | | | | | 96 | 06/CSB3 | I | | TxCLK6 | DUSCC-3 | 44/TRXCA | 21 | 08/STA3 ** | I | | | | | 47 | 22/STB3 ** | I | | RxCLK6 | DUSCC-3 | 43/RTXCA | 22 | 15/RTA3 ** | I | | | | | 20 | 23/RTB3 ** | I | | SG | --- | --- | 97 | 07/SG | - | +---------+---------+----------+-------+------------+-----+ +---------------------------------------------------------+ | Port 7, RS-422 | +---------+---------+----------+-------+------------+-----+ | Signal | Signal |DUSCC/CIO |100-Pin| 25-Pin/Name| I/O | | Name | Source | Pin/Name | No. | (* RS-449) | | +---------+---------+----------+-------+------------+-----+ | TxD7 | DUSCC-3 | 15/TXDB | 48 | 02/SDA3 | O | | | | | 49 | 24/SDB3 | O | | RxD7 | DUSCC-3 | 14/RXDB | 74 | 03/RDA3 | I | | | | | 25 | 17/RDB3 | I | |-RTS7 | DUSCC-3 | 09/-RTSBN| 73 | 04/RSA3 | O | | | | | 23 | 20/RSB3 | O | |-CTS7 | DUSCC-3 | 19/-CTSBN| 24 | 05/CSA3 | I | | | | | 50 | 06/CSB3 | I | | TxCLK7 | DUSCC-3 | 10/TRXCB | 99 | 08/STA3 ** | I | | | | | 75 | 22/STB3 ** | I | | RxCLK7 | DUSCC-3 | 11/RTXCB | 100 | 15/RTA3 ** | I | | | | | 98 | 23/RTB3 ** | I | | SG | --- | --- | 97 | 07/SG | - | +---------+---------+----------+-------+------------+-----+* RS-449 signal naming conventions are used. IBM makes no claims as to compatibility with RS-449.
** These signal pairs are terminated from line-to-line by a 120-ohm resistor.
The following figure shows the pinout configuration of the 100-pin D-shell female connector (K9B) on the interface board.
26 \ / 01 51 \ / 27 75 \ / 52 100 \ / 76The pin assignments for the 100-pin connector on the eight-port RS-422 interface board/A are listed in Table 25..
Table 25. Eight-Port RS-422-A Connector Pin Assignments
+---------+----+-------------------------+----------+ | Signal | I/O| 100-Pin Connector | 25-Pin | | Name | | (Ports 0-7) | Connector| | | | 0 1 2 3 4 5 6 7 | Pin Name | +---------+----+-------------------------+----------+ | TxD | O | 51 54 07 10 13 16 94 48 | 02/SDA | +---------+----+-------------------------+----------+ | | O | 52 55 08 11 14 17 95 49 | 24/SDB | +---------+----+-------------------------+----------+ | RxD | I | 02 05 83 86 89 92 46 74 | 03/RDA | +---------+----+-------------------------+----------+ | | I | 78 81 35 38 41 44 72 25 | 17/RDB | +---------+----+-------------------------+----------+ | -RTS | O | 01 04 82 85 88 91 45 73 | 04/RSA | +---------+----+-------------------------+----------+ | | O | 76 79 33 36 39 42 70 23 | 20/RSB | +---------+----+-------------------------+----------+ | -CTS | I | 77 80 34 37 40 43 71 24 | 05/CSA | +---------+----+-------------------------+----------+ | | I | 53 56 09 12 15 18 96 50 | 06/CSB | +---------+----+-------------------------+----------+ | TxCLK | I | 28 31 59 62 65 68 21 99 | 08/STA | +---------+----+-------------------------+----------+ | | I | 03 06 84 87 90 93 47 75 | 22/STB | +---------+----+-------------------------+----------+ | RxCLK | I | 29 32 60 63 66 69 22 100| 15/RTA | +---------+----+-------------------------+----------+ | | I | 27 30 58 61 64 67 20 98 | 23/RTB | +---------+----+-------------------------+----------+ | SG | -- | 19 19 26 26 57 57 97 97 | 07/GND | +---------+----+-------------------------+----------+
With All Ports Wrapped
An Eight-Port Cable is available as an option to support the Eight-Port RS-422 Interface Board/A. The Eight-Port Cable converts the 100-pin female D-shell connector (K9B) on the co-processor adapter to appropriate connector interfaces for external cabling. This cable is 1.2 meters (4 feet) long. It has a 100-pin male D-shell connector (K9A) on one end that attaches to the connector on the co-processor adapter. At the other end of the cable is a molded distribution box, containing eight 25-pin male D-shell connectors (K00-K07) that attach to external cabling.
The approximate dimensions of the distribution box are 203 mm (8 in.) long by 76 mm (3 in.) high by 38 mm (1.5 in.) deep.
Eight-Port Cable
+-----+ +-----+ +------------------+
| +-+ +-+ | | Port 0 (K00) |
| | | | | +------------+ |
|100-pin| |100-pin+-----------------------------+ \------------/ |
|female | | male +-----------------------------+ Port 1 (K01) |
| (K9B) | | (K9A) | Cable (1.2 m) | +------------+ |
| | | | | \------------/ |
| +-+ +-+ | | Port 2 (K02) |
+-----+ +-----+ | +------------+ |
Rear of | \------------/ |
Co-Processor | Port 3 (K03) |
Adapter | +------------+ |
| \------------/ |
| Port 4 (K04) |
| +------------+ |
| \------------/ |
| Port 5 (K05) |
+---------------------------+ | +------------+ |
1 \ . . . . . . . . . . . . . / 13 | \------------/ |
14 \ . . . . . . . . . . . . / 25 | Port 6 (K06) |
+-----------------------+ | +------------+ |
25-Pin D-Shell Connectors ---------->| \------------/ |
(K00 - K07) | Port 7 (K07) |
| +------------+ |
| \------------/ |
+------------------+
The following table shows the connections from connector
K9A to connectors K00 through K07.
+---------------------------------------------------------------+ | K9A to K00 through K07 Connections | +-----------++-----------++-----------++-----------++-----------+ |K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # | +-----------++-----------++-----------++-----------++-----------+ |01 K00-04||21 K06-08||41 K04-17||61 K03-23||81 K01-17| |02 K00-03||22 K06-15||42 K05-20||62 K03-08||82 K02-04| |03 K00-22||23 K07-20||43 K05-05||63 K03-15||83 K02-03| |04 K01-04||24 K07-05||44 K05-17||64 K04-23||84 K02-22| |05 K01-03||25 K07-17||45 K06-04||65 K04-08||85 K03-04| |06 K01-22||26 Gnd 2&3||46 K06-03||66 K04-15||86 K03-03| |07 K02-02||27 K00-23||47 K06-22||67 K05-23||87 K03-22| |08 K02-24||28 K01-08||48 K07-02||68 K05-08||88 K04-04| |09 K02-06||29 K00-15||49 K07-24||69 K05-15||89 K04-03| |10 K03-02||30 K01-23||50 K07-06||70 K06-20||90 K04-22| |11 K03-24||31 K01-08||51 K00-02||71 K06-05||91 K05-04| |12 K03-06||32 K01-15||52 K00-24||72 K06-17||92 K05-03| |13 K04-02||33 K02-20||53 K00-06||73 K07-04||93 K05-22| |14 K04-24||34 K02-05||54 K01-02||74 K07-03||94 K06-02| |15 K04-06||35 K02-17||55 K01-24||75 K07-22||95 K06-24| |16 K05-02||36 K03-20||56 K01-06||76 K00-20||96 K06-06| |17 K05-24||37 K03-05||57 Gnd 4&5||77 K00-05||97 Gnd 6&7| |18 K05-06||38 K03-17||58 K02-23||78 K00-17||98 K07-23| |19 Gnd 0&1||39 K04-20||59 K02-08||79 K01-20||99 K07-08| |20 K06-23||40 K04-05||60 K02-15||80 K01-05||100 K07-15| +-----------++-----------++-----------++-----------++-----------+
The following cabling recommendations apply for all cables that are to be constructed for use with the co-processor adapter. Correct operation of any interface depends on several factors that should be taken into consideration during installation.
Typical physical characteristics for this cable are as follows. Consult cable manufacturer catalogs for further information.
A surge protection adapter can be used to provide voltage suppression circuitry in conjunction with the Eight-Port RS-422 Interface Board/A and the Eight-Port Cable for each port where voltage suppression is desired. This adapter has two 25-pin D-shell connectors, which interconnect the appropriate interface cable connector to the cabling.
An optional diagnostic wrap plug is available with the Hardware Maintenance Library for diagnosing problems with the eight-port RS-422 interface board/A, as well as the co-processor adapter. This 100-pin male wrap plug (P/N 57F0678) is designed to wrap all signals used for RS-422-A operation at connector K9B. (No cable is associated with this wrap plug.)
The following table shows all wrapped signal connections.
+-----------------------------------------------------------+ | Eight-Port Interface Board/A Wrap Plug Connections | +----+-------------------+----------------------------------+ | | Connector | | |Port| K9B Pins | Signals Wrapped | +----+-------------------+----------------------------------+ | | 51 - 02 | SDA0 -> RDA0 | | | 52 - 78 | SDB0 -> RDB0 | | 0 | 01 - 77 - 28 - 29 | RSA0 -> CSA0 -> STA0 -> RTA0 | | | 76 - 53 - 03 - 27 | RSB0 -> CSB0 -> STB0 -> RTB0 | +----+-------------------+----------------------------------+ | | 54 - 05 | SDA1 -> RDA1 | | | 55 - 81 | SDB1 -> RDB1 | | 1 | 04 - 80 - 31 - 32 | RSA1 -> CSA1 -> STA1 -> RTA1 | | | 79 - 56 - 06 - 30 | RSB1 -> CSB1 -> STB1 -> RTB1 | +----+-------------------+----------------------------------+ | | 07 - 83 | SDA2 -> RDA2 | | | 08 - 35 | SDB2 -> RDB2 | | 2 | 82 - 34 - 59 - 60 | RSA2 -> CSA2 -> STA2 -> RTA2 | | | 33 - 09 - 84 - 58 | RSB2 -> CSB2 -> STB2 -> RTB2 | +----+-------------------+----------------------------------+ | | 10 - 86 | SDA3 -> RDA3 | | | 11 - 38 | SDB3 -> RDB3 | | 3 | 85 - 37 - 62 - 63 | RSA3 -> CSA3 -> STA3 -> RTA3 | | | 36 - 12 - 87 - 61 | RSB3 -> CSB3 -> STB3 -> RTB3 | +----+-------------------+----------------------------------+ | | 13 - 89 | SDA4 -> RDA4 | | | 14 - 41 | SDB4 -> RDB4 | | 4 | 88 - 40 - 65 - 66 | RSA4 -> CSA4 -> STA4 -> RTA4 | | | 39 - 15 - 90 - 64 | RSB4 -> CSB4 -> STB4 -> RTB4 | +----+-------------------+----------------------------------+ | | 16 - 92 | SDA5 -> RDA5 | | | 17 - 44 | SDB5 -> RDB5 | | 5 | 91 - 43 - 68 - 69 | RSA5 -> CSA5 -> STA5 -> RTA5 | | | 42 - 18 - 93 - 67 | RSB5 -> CSB5 -> STB5 -> RTB5 | +----+-------------------+----------------------------------+ | | 94 - 46 | SDA6 -> RDA6 | | | 95 - 72 | SDB6 -> RDB6 | | 6 | 45 - 71 - 21 - 22 | RSA6 -> CSA6 -> STA6 -> RTA6 | | | 70 - 96 - 47 - 20 | RSB6 -> CSB6 -> STB6 -> RTB6 | +----+-------------------+----------------------------------+ | | 48 - 74 | SDA7 -> RDA7 | | | 49 - 25 | SDB7 -> RDB7 | | 7 | 73 - 24 - 99 - 100| RSA7 -> CSA7 -> STA7 -> RTA7 | | | 23 - 50 - 75 - 98 | RSB7 -> CSB7 -> STB7 -> RTB7 | +----+-------------------+----------------------------------+
An optional diagnostic wrap plug for the eight-port cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the interface cable. This 25-pin female wrap plug (P/N 33F8985) is used for RS-422-A operation on ports 0 through 7.
The following table shows the signals wrapped within the wrap plug. The wrap connection is made from each transmit output signal and looped back to the corresponding receive input signal on the 25-pin D-shell connector.
+------------------------------------------------+ | Wrap Connections for Ports 0 through 7 | +--------------------+---------------------------+ | Associated Pins | Signals Wrapped | +--------------------+---------------------------+ | 02 - 03 | SDA -> RDA | | 24 - 17 | SDB -> RDB | | 04 - 05 - 08 - 15 | RSA -> CSA -> STA -> RTA | | 20 - 06 - 22 - 23 | RSB -> CSB -> STB -> RTB | +--------------------+---------------------------+
This chapter contains the following information for the Selectable Interface Board/A and related external devices:
The Selectable Interface Board/A contains the signal conditioning circuitry to convert TTL logic levels to the required protocol logic levels (and vice versa) for up to four serial ports.
The following communications interfaces are supported:
All ports can support asynchronous or synchronous communication, except for RS-422-A operation on port 2, which is asynchronous data only.
Protocols for these electrical interfaces are user programmable.
The interface board connects to the co-processor adapter by a pair of 60-pin connectors. Signals exit the interface board through the 78-pin D-shell connector at one end of the interface board.
Clocking is supported on all ports, except port 2 when it is operating in the RS-422-A communications mode.
This interface board has a data rate of up to 64K baud, duplex, with all four ports operating concurrently. A data rate of up to 2.048M baud, duplex, can be attained when a single synchronous port is operating in the V.35 (4) or the RS-422-A mode.
The ID for this interface board is BFh.
The voltage requirements for this board are +5V, +12V, and -12V.
The maximum cable lengths that are supported at 64k baud for the various communications protocols are:
+---------+---------+-------+---------+ | Protoco | Length | Length (feet) | | l | (meters | :ethd. | | | ) | | +---------+---------+-------+---------+ | RS-232- | 15.2 | 50 | | C | | | +---------+---------+-------+---------+ | V.35 | 15.2 | 50 | +---------+---------+-------+---------+ | RS-422- | 122 | 400 | | A | | | +---------+---------+-------+---------+ | X.21 | 122 | 400 | +---------+---------+-----------------+Above 64K baud, the maximum cable lengths may be less than listed here.
Cables are not supported for outdoor operation.
The following tables provide the signal relationships between the DUSCCs, the CIOs, and the serial ports. Input and output direction is given relative to the DUSCCs and the CIOs.
+---------------------------------------------------------------------------+ | Port 0 - RS-232, RS-422, X.21, V.35 | +----------+-----+---------+----------+-------------------------------------+ | Signal | | Signal | DUSCC/CIO| Function | | Name | I/O | Source | Pin/Name | (Interface Supported) | +----------+-----+---------+----------+-------------------------------------+ | +TXD0 | O | DUSCC-0 | 39/TXDA | Transmit data (all) | | +RXD0 | I | DUSCC-0 | 40/RXDA | Receive data (all) | | +RXCLK0 | I | DUSCC-0 | 43/RTXCA | Receive clock (all) | | +TXCLK0 | I | DUSCC-0 | 44/TRXCA | Transmit clock (all except X.21) | | | | | | (see Note 1) | | +DTECLK0 | O | DUSCC-0 | 44/TRXCA | DTE clock (RS-232-C) | | -RTS0 | O | DUSCC-0 | 45/-RTSA | Request to send (RS-232-C, V.35) | | | | | | (see Note 2) | | -CTS0 | I | DUSCC-0 | 35/-CTSA | Clear to send (RS-232-C, V.35) | | -DCD0 | I | DUSCC-0 | 42/-DCDA | Data carrier detect (RS-232-C, V.35)| | -DTR0 | O | CIO-0 | 37/PA-0 | Data terminal ready (RS-232-C,V.35) | | -HRS0 | O | CIO-0 | 36/PA-1 | Half-rate select (RS-232-C) | | -DSR0 | I | CIO-0 | 31/PA-6 | Data set ready (RS-232-C, V.35) | | -RI0 | I | CIO-0 | 30/PA-7 | Ring indicate (RS-232-C) | | +CA0 | O | EN_REG | /EN-0 | Control (X.21) | | Reserved | O | EN_REG | /EN-2 | Always program with a logic 1 | | Reserved | O | EN_REG | /EN-3 | Always program with a logic 0 | | +RXDST1 | I | CIO-1 | 21/PC-0 | X.21 receive data status bit 1 | | +RXDST2 | I | CIO-1 | 22/PC-1 | X.21 receive data status bit 2 | | +IA0 | I | CIO-1 | 24/PC-3 | Indicate (X.21) | | -EN0/232 | O | CIO-0 | 35/PA-2 | Enable port 0 RS-232-C | | -EN0/T232| O | CIO-0 | 34/PA-3 | Enable RS-232-C transmit clock from | | | | | | DCE | | -EN0/V35 | O | CIO-0 | 33/PA-4 | Enable port 0 V.35 | | -EN0/X21 | O | EN_REG | /EN-1 | Enable RS-422-A/X.21 (RS-422-A/X.21)| | +EN0/422 | O | CIO-0 | 32/PA-5 | Enable port 0 RS-422-A/X.21 | | | | | | (see Note 3) | +----------+-----+---------+----------+-------------------------------------+Notes:
+---------------------------------------------------------------------------+ | Port 1 - RS-232, V.35 | +----------+-----+---------+----------+-------------------------------------+ | Signal | | Signal | DUSCC/CIO| Function | | Name | I/O | Source | Pin/Name | (Interface Supported) | +----------+-----+---------+----------+-------------------------------------+ | +TXD1 | O | DUSCC-0 | 15/TXDB | Transmit data (RS-232-C, V.35) | | +RXD1 | I | DUSCC-0 | 14/RXDB | Receive data (RS-232-C, V.35) | | +RXCLK1 | I | DUSCC-0 | 11/RTXCB | Receive clock (RS-232-C, V.35) | | +TXCLK1 | I | DUSCC-0 | 10/TRXCB | Transmit clock (RS-232-C, V.35) | | +DTECLK1 | O | DUSCC-0 | 10/TRXCB | DTE clock (RS-232-C) | | -RTS1 | O | DUSCC-0 | 09/-RTSB | Request to send (RS-232-C, V.35) | | -CTS1 | I | DUSCC-0 | 19/-CTSB | Clear to send (RS-232-C, V.35) | | -DCD1 | I | DUSCC-0 | 12/-DCDB | Data carrier detect (RS-232-C, V.35)| | -DTR1 | O | CIO-0 | 10/PB-0 | Data terminal ready (RS-232-C, V.35)| | -HRS1 | O | CIO-0 | 11/PB-1 | Half-rate select (RS-232-C) | | -DSR1 | I | CIO-0 | 16/PB-6 | Data set ready (RS-232-C, V.35) | | -RI1 | I | CIO-0 | 17/PB-7 | Ring indicate (RS-232-C) | | -EN1/232 | O | CIO-0 | 12/PB-2 | Enable port 1 RS-232-C | | -EN1/T232| O | CIO-0 | 13/PB-3 | Enable RS-232-C transmit clock from | | | | | | DCE | | -EN1/V35 | O | CIO-0 | 14/PB-4 | Enable port 1 V.35 receiver | +----------+-----+---------+----------+-------------------------------------+ +---------------------------------------------------------------------------+ | Port 2 - RS-232, RS-422 (ASYNC data only) | +----------+-----+---------+----------+-------------------------------------+ | Signal | | Signal | DUSCC/CIO| Function | | Name | I/O | Source | Pin/Name | (Interface Supported) | +----------+-----+---------+----------+-------------------------------------+ | +TXD2 | O | DUSCC-1 | 39/TXDA | Transmit data (RS-232-C, RS422-A) | | +RXD2 | I | DUSCC-1 | 40/RXDA | Receive data (RS-232-C, RS422-A) | | +RXCLK2 | I | DUSCC-1 | 43/RTXCA | Receive clock (RS-232-C) | | +TXCLK2 | I | DUSCC-1 | 44/TRXCA | Transmit clock (RS-232-C) | | +DTECLK2 | O | DUSCC-1 | 44/TRXCA | DTE clock (RS-232-C) | | -RTS2 | O | DUSCC-1 | 45/-RTSA | Request to send (RS-232-C) | | -CTS2 | I | DUSCC-1 | 35/-CTSA | Clear to send (RS-232-C) | | -DCD2 | I | DUSCC-1 | 42/-DCDA | Data carrier detect (RS-232-C) | | -DTR2 | O | CIO-1 | 37/PA-0 | Data terminal ready (RS-232-C) | | -HRS2 | O | CIO-1 | 36/PA-1 | Half-rate select (RS-232-C) | | -DSR2 | I | CIO-1 | 31/PA-6 | Data set ready (RS-232-C) | | -RI2 | I | CIO-1 | 30/PA-7 | Ring indicate (RS-232-C) | | -EN2/232 | O | CIO-1 | 35/PA-2 | Enable port 2 RS-232-C | | -EN2/T232| O | CIO-1 | 34/PA-3 | Enable RS-232-C transmit clock from | | | | | | DCE | | +EN2/422 | O | CIO-1 | 33/PA-5 | Enable port 2 RS-422-A | +----------+-----+---------+----------+-------------------------------------+ +---------------------------------------------------------------------------+ | Port 3 - RS-232 | +----------+-----+---------+----------+-------------------------------------+ | Signal | | Signal | DUSCC/CIO| Function | | Name | I/O | Source | Pin/Name | (Interface Supported) | +----------+-----+---------+----------+-------------------------------------+ | TXD3 | O | DUSCC-1 | 15/TXDB | Transmit data (RS-232-C) | | RXD3 | I | DUSCC-1 | 14/RXDB | Receive data (RS-232-C) | | RXCLK3 | I | DUSCC-1 | 11/RTXCB | Receive clock (RS-232-C) | | TXCLK3 | I | DUSCC-1 | 10/TRXCB | Transmit clock (RS-232-C) | | DTECLK3 | O | DUSCC-1 | 10/TRXCA | DTE clock (RS-232-C) | | RTS3 | O | DUSCC-1 | 09/-RTSB | Request to send (RS-232-C) | | CTS3 | I | DUSCC-1 | 19/-CTSB | Clear to send (RS-232-C) | | DCD3 | I | DUSCC-1 | 12/-DCDB | Data carrier detect (RS-232-C) | | DTR3 | O | CIO-1 | 10/PB-0 | Data terminal ready (RS-232-C) | | DSR3 | I | CIO-1 | 16/PB-6 | Data set ready (RS-232-C) | | RI3 | I | CIO-1 | 17/PB-7 | Ring indicate (RS-232-C) | | EN3/T232 | O | CIO-1 | 13/PB-3 | Enable RS-232-C transmit clock from | | | | | | DCE | +----------+-----+---------+----------+-------------------------------------+
In the following table, it is assumed that all CIO Data Path Polarity Register bits are set as inverting. (The Realtime Control Microcode initially sets these bits as inverting.) Bits not shown are either inputs or should remain unchanged.
+-------------------------------------------------------------+ | Port Enabling Information (Ports 0-3) | +-----------------+-----------+-----------+-------------------+ | Interface | CIO/ENREG | Bit=Value | Signal Name | +-----------------+-----------+-----------+-------------------+ | PORT 0 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-0 | PA2=1 | -EN0/232 | | with outbound | CIO-0 | PA3=0 | -EN0/T232 | | transmit clock | CIO-0 | PA4=0 | -EN0/V35 | | | CIO-0 | PA5=1 | +EN0/422 | | | ENREG | D1=1 | -EN0/X21 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-0 | PA2=1 | -EN0/232 | | with inbound | CIO-0 | PA3=1 | -EN0/T232 | | transmit clock | CIO-0 | PA4=0 | -EN0/V35 | | | CIO-0 | PA5=1 | +EN0/422 | | | ENREG | D1=1 | -EN0/X21 | +-----------------+-----------+-----------+-------------------+ | RS-422-A | CIO-0 | PA2=0 | -EN0/232 | | | CIO-0 | PA3=0 | -EN0/T232 | | | CIO-0 | PA4=0 | -EN0/V35 | | | CIO-0 | PA5=0 | +EN0/422 | | | CIO-1 | PB2=1 | +BLOCK (Note 1) | | | ENREG | D1=1 | -EN0/X21 | +-----------------+-----------+-----------+-------------------+ | X.21 | CIO-0 | PA2=0 | -EN0/232 | | | CIO-0 | PA3=0 | -EN0/T232 | | | CIO-0 | PA4=0 | -EN0/V35 | | | CIO-0 | PA5=0 | +EN0/422 (Note 2) | | | CIO-1 | PB2=1 | +BLOCK (Note 1) | | | ENREG | D1=0 | -EN0/X21 | | | ENREG | D2=1 | -WRPDIAG | +-----------------+-----------+-----------+-------------------+ | V.35 | CIO-0 | PA2=0 | -EN0/232 | | | CIO-0 | PA3=0 | -EN0/T232 | | | CIO-0 | PA4=1 | -EN0/V35 | | | CIO-0 | PA5=1 | +EN0/422 | | | CIO-1 | PB2=1 | +BLOCK (Note 1) | | | ENREG | D1=1 | -EN0/X21 | +-----------------+-----------+-----------+-------------------+ | PORT 1 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-0 | PB2=1 | -EN1/232 | | with outbound | CIO-0 | PB3=0 | -EN1/T232 | | transmit clock | CIO-0 | PB4=0 | -EN1/V35 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-0 | PB2=1 | -EN1/232 | | with inbound | CIO-0 | PB3=1 | -EN1/T232 | | transmit clock | CIO-0 | PB4=0 | -EN1/V35 | +-----------------+-----------+-----------+-------------------+ | V.35 | CIO-0 | PB2=0 | -EN1/232 | | | CIO-0 | PB3=0 | -EN1/T232 | | | CIO-0 | PB4=1 | -EN1/V35 | | | CIO-1 | PB2=1 | +BLOCK (Note 1) | +-----------------+-----------+-----------+-------------------+ | PORT 2 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-1 | PA2=1 | -EN2/232 | | with outbound | CIO-1 | PA3=0 | +EN2/T232 | | transmit clock | CIO-1 | PA5=1 | +EN2/422 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-1 | PA2=1 | -EN2/232 | | with inbound | CIO-1 | PA3=1 | +EN2/T232 | | transmit clock | CIO-1 | PA5=1 | +EN2/422 | +-----------------+-----------+-----------+-------------------+ | RS-422-A | CIO-1 | PA2=0 | -EN2/232 | | | CIO-1 | PA3=0 | -EN2/T232 | | | CIO-1 | PA5=0 | +EN2/422 | +-----------------+-----------+-----------+-------------------+ | PORT 3 | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-1 | PB3=0 | -EN3/T232 | | with outbound | | | | | transmit clock | | | | +-----------------+-----------+-----------+-------------------+ | RS-232-C | CIO-1 | PB3=1 | -EN3/T232 | | with inbound | | | | | transmit clock | | | | +-----------------+-----------+-----------+-------------------+Notes:
The X.21 pattern recognition logic detects state changes in the X.21 protocol. The CCITT specification for X.21 uses changes in the Receive Data and the Indicate lines to signify that a state change has occurred. The X.21 pattern recognition logic monitors these lines to detect the following patterns:
In the following table, it is assumed that all CIO Data Path Polarity Register bits are set as inverting.
+--------+--------+-----------------------+ | RXDST0 | RXDST1 | Receive Data Status | +--------+--------+-----------------------+ | 1 | 1 | All 0s | | 1 | 0 | Alternating 1s and 0s | | 0 | 1 | Alternating 1s and 0s | | 0 | 0 | All 1s | +--------+--------+-----------------------+Two interrupts occur that are not the result of X.21 network state changes; both of these interrupts are used for diagnostic purposes. The first interrupt is generated when -EN0/X21 goes active. The second interrupt is generated 16 clock pulses after -EN0/X21 goes active. The status bits (RXDST0 and RXDST1) are set by the second interrupt and can be ignored.
X.21 Bit Pattern Recognition Interrupt
Note:
Be sure to store the address of the ISR at address 0x1F0 (location of ISR pointer for interrupt vector 0x7c)."Sample" Interrupt Service Routine (ISR)
call EXTERNAL_INT routine(5)
call int_ntry routine(5)
check status of INDICATE
if INDICATE is ON
then do necessary processing
else read status bits and do necessary processing
output a byte to DUSCC2 EOI register
(see Appendix B, DMAEOI)
call nseoi routine(5)
call int_exit routine(5)
call PREEMPTCD routine(5)
A Selectable Cable is available as an option to support the Selectable Interface Board/A. The Selectable Cable converts the 78-pin female D-shell connector (K9B) on the co-processor adapter to appropriate connector interfaces for external cabling. This cable is 3.1 meters (10 feet) long. It has a 78-pin male D-shell connector (K9A) on one end that attaches to the connector on the co-processor adapter. At the other end of the cable is a molded distribution box, containing six 25-pin male D-shell connectors (K01, K03, K04, K06, K07, K08) and three 15-pin male connectors (K00, K02, K05) that attach to external cabling.
The approximate dimensions of the distribution box are 202 mm (9.5 in.) long by 65 mm (2.5 in.) high, by 35 mm (1.4 in.) deep.
Selectable Cable
+------------------+
+-----+ +-----+ | Port 0 (K00) |
| +-+ +-+ | | +------------+ |
| | | | | \----------/ |
| 78-pin| | 78-pin+-----------------------------+ Port 0 (K01) |
|female | | male +-----------------------------+ +------------+ |
| (K9B) | | (K9A) | Cable (3.1 m) | \----------/ |
| | | | | Port 0 (K02) |
| +-+ +-+ | | +------------+ |
+-----+ +-----+ | \----------/ |
Rear of | Port 0 (K03) |
Co-Processor | +------------+ |
Adapter | \----------/ |
| Port 1 (K04) |
| +------------+ |
| \----------/ |
| Port 1 (K05) |
Notes: | +------------+ |
1. Connectors K01, K03, K04, K06, | \----------/ |
K07, and K08 are 25-pin D-shell | Port 3 (K06) |
male connectors. | +------------+ |
2. Connectors K00, K02, and K05 are | \----------/ |
15-pin D-shell male connectors. | Port 2 (K07) |
| +------------+ |
| \----------/ |
| Port 2 (K08) |
| +------------+ |
| \----------/ |
+------------------+
The following table shows the connections for the Selectable Cable from connector K9A to connectors K00 through K08.
+---------------------------------------------------------------+ | K9A to K00 through K08 Connections | +-----------++-----------++-----------++-----------++-----------+ |K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # | +-----------++-----------++-----------++-----------++-----------+ |01-+>K00-03||18-+>K00-10||32 K06-22||46 K06-23||62 K01-17| | +>K01-04|| +>K02-05||33 K08-05||47 K07-20||63-+>K04-04| |02 K01-03|| +>K03-15||34 K04-24||48 K07-05|| +>K05-03| |03 K01-22||19-+>K00-11||35 K05-04||49 K05-09||64 K04-03| |04 K04-02|| +>K02-04||36 K00-09||50 K06-20||65 K04-22| |05 No conn|| +>K03-05||37-+>K02-02||51 K06-05||66 K07-02| |06-+>K04-06||20 K02-03|| +>K03-04||52 K08-02||67 K06-07| | +>K05-06||21 K01-23||38-+>K00-14||53 K00-02||68 K07-06| |07-+>K04-07||22-+>K00-07|| +>K02-06||54 K07-24||69 K06-02| | +>K05-08|| +>K01-08|| +>K03-17||55 K05-13||70 K07-15| |08-+>K07-07||23 K01-15||39 K05-10||56 K04-15||71 K06-06| | +>K08-07||24-+>K04-20||40 K01-02||57-+>K00-12||72 K08-03| |09 K07-08|| +>K05-15||41 No conn|| +>K02-12||73 K06-24| |10 K07-17||25-+>K04-05||42-+>K00-06|| +>K03-12||74 K05-14| |11 K07-23|| +>K05-05|| +>K01-06||58-+>K00-04||75 K06-15| |12 K06-08||26 K04-17||43-+>K00-08|| +>K02-11||76-+>K02-09| |13 K08-04||27 K07-04|| +>K01-07|| +>K03-03|| +>K03-02| |14 K05-02||28 K07-03|| +>K02-08||59 K02-10||77-+>K00-13| |15 K01-24||29 K07-22|| +>K03-07||60-+>K00-15|| +>K02-13| |16 K05-12||30 K06-04||44 K04-23|| +>K00-20|| +>K03-09| |17 K06-17||31 K06-03||45-+>K04-08||61-+>K00-05||78 K05-11| | || || +>K05-07||61 +>K01-05|| | +-----------++-----------++-----------++-----------++-----------+
The 78-pin D-shell female connector on the Selectable Interface Board/A is as follows.
20 \ / 01
39 \ / 21
59 \ / 40
78 \ / 60
A typical 25-pin D-shell male connector on the Selectable Cable
is as follows.
01 \ / 13 14 \ / 25A typical 15-pin D-shell male connector on the Selectable Cable is as follows.
01 \ / 08 09 \ / 15
Table 27. through Table 30. list the pin assignments for the 78-pin connector on the Selectable Interface Board/A and the corresponding connectors on the Selectable Cable. These tables also identify the direction (I for input and O for output) that the signal is driven with respect to the interface board. Table 27. RS-232-C Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 25-Pin | | Name | | Connector | Connector| | | | Ports 0-3 |1, 4, 6, 7| | | | | | | | | 0 1 2 3 | | +--------+----+-----------------+----------+ | TXD | O | 40 04 66 69 | 02 | +--------+----+-----------------+----------+ | RXD | I | 02 64 28 31 | 03 | +--------+----+-----------------+----------+ | RTS | O | 01 63 27 30 | 04 | +--------+----+-----------------+----------+ | CTS | I | 61 25 48 51 | 05 | +--------+----+-----------------+----------+ | DCD | I | 22 45 09 12 | 08 | +--------+----+-----------------+----------+ | DTR | O | 60 24 47 50 | 20 | +--------+----+-----------------+----------+ | DSR | I | 42 06 68 71 | 06 | +--------+----+-----------------+----------+ | HRS | O | 21 44 11 | 23 | | | | | (1, 4, 7)| +--------+----+-----------------+----------+ | RI | I | 03 65 29 32 | 22 | +--------+----+-----------------+----------+ | DTECLK | O | 15 34 54 73 | 24 | +--------+----+-----------------+----------+ | TCLKIN | I | 23 56 70 75 | 15 | +--------+----+-----------------+----------+ | RCLKIN | I | 62 26 10 17 | 17 | +--------+----+-----------------+----------+ | SG | -- | 43 07 08 67 | 07 | +--------+----+-----------------+----------+Table 28. RS-422-A Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 25-Pin | | Name | | Connector | Connector| | | | Ports 0, 2 | 3, 8 | | | | 0 2 | | +--------+----+-----------------+----------+ | TxD | O | 37 13 | 02 02 SDA| +--------+----+-----------------+----------+ | | O | 76 52 | 04 04 SDB| +--------+----+-----------------+----------+ | RxD | I | 19 33 | 03 03 RDA| +--------+----+-----------------+----------+ | | I | 58 72 | 05 05 RDB| +--------+----+-----------------+----------+ | TxCLK | I | 18 -- | 23 -- STA| +--------+----+-----------------+----------+ | | I | 57 -- | 24 -- STB| +--------+----+-----------------+----------+ | RxCLK | I | 38 -- | 22 -- RTA| +--------+----+-----------------+----------+ | | I | 77 -- | 17 -- RTB| +--------+----+-----------------+----------+ | SGND | -- | 43 08 | 07 07 GND| +--------+----+-----------------+----------+Table 29. V.35 Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 15-Pin | | Name | | Connector | Connector| | | | Ports 0-1 | 0, 5 | | | | 0 1 | | +--------+----+-----------------+----------+ | TXDA | O | 36 49 | 09 | +--------+----+-----------------+----------+ | TXDB | O | 53 14 | 02 | +--------+----+-----------------+----------+ | RXDA | I | 19 78 | 11 | +--------+----+-----------------+----------+ | RXDB | I | 58 35 | 04 | +--------+----+-----------------+----------+ | TXCA | I | 18 39 | 10 | +--------+----+-----------------+----------+ | TXCB | I | 57 16 | 12 | +--------+----+-----------------+----------+ | RXCA | I | 38 74 | 14 | +--------+----+-----------------+----------+ | RXCB | I | 77 55 | 13 | +--------+----+-----------------+----------+ | RTS | O | 01 63 | 03 | +--------+----+-----------------+----------+ | CTS | I | 61 25 | 05 | +--------+----+-----------------+----------+ | DCD | I | 22 45 | 07 | +--------+----+-----------------+----------+ | DSR | I | 42 06 | 06 | +--------+----+-----------------+----------+ | DTR | O | 60 24 | 15 | +--------+----+-----------------+----------+ | SGND | -- | 43 07 | 08 | +--------+----+-----------------+----------+Table 30. X.21 Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 15-Pin | | Name | | Connector | Connector| | | | Port 0 | 2 | | | | 0 | | +--------+----+-----------------+----------+ | T(A) | O | 37 | 02 | +--------+----+-----------------+----------+ | T(B) | O | 76 | 09 | +--------+----+-----------------+----------+ | R(A) | I | 19 | 04 | +--------+----+-----------------+----------+ | R(B) | I | 58 | 11 | +--------+----+-----------------+----------+ | C(A) | O | 20 | 03 | +--------+----+-----------------+----------+ | C(B) | O | 59 | 10 | +--------+----+-----------------+----------+ | I(A) | I | 18 | 05 | +--------+----+-----------------+----------+ | I(B) | I | 57 | 12 | +--------+----+-----------------+----------+ | S(A) | I | 38 | 06 | +--------+----+-----------------+----------+ | S(B) | I | 77 | 13 | +--------+----+-----------------+----------+ | SG | -- | 43 | 08 | +--------+----+-----------------+----------+
A one-port X.21 cable is available as an option to support the Selectable Interface Board. This cable converts the 78-pin female D-shell connector (K9B) on the Selectable Interface Board to a 15-pin interface for support of X.21 operation on port 0.
The 78-pin D-shell male connector on the one-port X.21 cable is as follows.
01 \ / 20
21 \ / 39
40 \ / 59
60 \ / 78
The 15-pin D-shell male connector on the one-port X.21 cable
is as follows.
01 \ / 08 09 \ / 15
The pin assignments for the one-port X.21 cable are listed in Table 31.. This table also identifies the direction (I for input and O for output) that the signal is driven with respect to the interface board.
Table 31. X.21 Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 15-Pin | | | | Connector | Connector| | | | Port 0 | | | | | 0 | | +--------+----+-----------------+----------+ | T(A) | O | 37 | 02 | +--------+----+-----------------+----------+ | T(B) | O | 76 | 09 | +--------+----+-----------------+----------+ | R(A) | I | 19 | 04 | +--------+----+-----------------+----------+ | R(B) | I | 58 | 11 | +--------+----+-----------------+----------+ | C(A) | O | 20 | 03 | +--------+----+-----------------+----------+ | C(B) | O | 59 | 10 | +--------+----+-----------------+----------+ | I(A) | I | 18 | 05 | +--------+----+-----------------+----------+ | I(B) | I | 57 | 12 | +--------+----+-----------------+----------+ | S(A) | I | 38 | 06 | +--------+----+-----------------+----------+ | S(B) | I | 77 | 13 | +--------+----+-----------------+----------+ | SGND | -- | 43 | 08 | +--------+----+-----------------+----------+ | FGND | -- | Cable shield | 01 | +--------+----+-----------------+----------+
A one-port V.35 cable is available as an option to support the Selectable Interface Board. This cable converts the 78-pin female D-shell connector (K9B) on the Selectable Interface Board to a 34-pin interface for support of high-speed (>1M baud) V.35 operation on port 0.
The 78-pin D-shell male connector on the one-port V.35 cable is as follows.
01 \ / 20
21 \ / 39
40 \ / 59
60 \ / 78
The 34-pin male connector on the one-port V.35 cable
is as follows.
/O C H M S WAAEEKK O\ | | | A E K P U YCCHHMM | |O O| | D J N T XBBFFLL | | | \OB F L R V ZDDJJNNO/
The pin assignments for the one-port V.35 cable are listed in Table 32.. This table also identifies the direction (I for input and O for output) that the signal is driven with respect to the interface board. Table 32. V.35 Connector Pin Assignments
+--------+----+-----------------+----------+ | Signal | I/O| 78-Pin | 34-Pin | | Name | | Connector | Connector| | | | (Port 0) | | | | | 0 | | +--------+----+-----------------+----------+ | TXDA | O | 36 | P | +--------+----+-----------------+----------+ | TXDB | O | 53 | S | +--------+----+-----------------+----------+ | RXDA | I | 19 | R | +--------+----+-----------------+----------+ | RXDB | I | 58 | T | +--------+----+-----------------+----------+ | TXCA(6)| I | 57 | Y | +--------+----+-----------------+----------+ | TXCB(6)| I | 18 | AA | +--------+----+-----------------+----------+ | RXCA | I | 38 | V | +--------+----+-----------------+----------+ | RXCB | I | 77 | X | +--------+----+-----------------+----------+ | RTS | O | 01 | C | +--------+----+-----------------+----------+ | CTS | I | 61 | D | +--------+----+-----------------+----------+ | DCD | I | 22 | F | +--------+----+-----------------+----------+ | DSR | I | 42 | E | +--------+----+-----------------+----------+ | DTR | O | 60 | H | +--------+----+-----------------+----------+ | SGND | -- | 43 | B | +--------+----+-----------------+----------+ | FGND | -- | Cable ground | A | +--------+----+-----------------+----------+
An optional diagnostic wrap plug is available with the Hardware Maintenance Library for diagnosing problems with the Selectable Interface Board/A, as well as the co-processor adapter. This 78-pin male wrap plug (P/N 40F9902) is designed to wrap all signals at connector K9B. (No cable is associated with this wrap plug.) The following tables show all wrapped signal connections for ports 0 through 3.
+---------------------------------------------------------+ | Port 0 - Wrapped Signal Connections | +------+------------------+-------------------------------+ | | Connector | | | Port | K9B Pins | Signals Wrapped | +------+------------------+-------------------------------+ | RS-232-C | +------+------------------+-------------------------------+ | | 40 - 02 | TXD0 -> RXD0 | | | 01 - 22 - 61 | RTS0 -> DCD0 -> CTS0 | | 0 | 60 - 42 - 23 | DTR0 -> DSR0 -> TCLKIN0 | | | 15 - 62 | DTECLK0 -> RCLKIN0 | | | 21 - 03 | HRS0 -> RI0 | +------+------------------+-------------------------------+ | RS-422-A | +------+------------------+-------------------------------+ | | 37 - 19 - 38 | +TxD0 -> +RxDA0 -> +RxCLK0 | | 0 | 76 - 58 - 77 | -TxD0 -> -RxDA0 -> -RxCLK0 | | | 20 - 18 | C(A)0 -> +TxCLK0 | | | 59 - 57 | C(B)0 -> -TxCLK0 | +------+------------------+-------------------------------+ | V.35 | +------+------------------+-------------------------------+ | | 36 - 19 - 38 | TXDA0 -> RXDA0 -> RXCA0 | | 0 | 53 - 58 - 77 | TXDB0 -> RXDB0 -> RXCB0 | | | 01 - 22 - 61 | RTS0 -> DCD0 -> CTS0 | | | 60 - 42 | DTR0 -> DSR0 | +------+------------------+-------------------------------+ | X.21 | +------+------------------+-------------------------------+ | | 37 - 19 - 38 | T(A)0 -> R(A)0 -> S(A)0 | | 0 | 76 - 58 - 77 | T(B)0 -> R(B)0 -> S(B)0 | | | 20 - 18 | C(A)0 -> I(A)0 | | | 59 - 57 | C(B)0 -> I(B)0 | +------+------------------+-------------------------------+ +---------------------------------------------------------------+ | Port 1 - Wrapped Signal Connections | +------+------------------+-------------------------------------+ | | Connector | | | Port | K9B Pins | Signals Wrapped | +------+------------------+-------------------------------------+ | RS-232-C | +------+------------------+-------------------------------------+ | | 04 - 64 | TXD1 -> RXD1 | | | 63 - 45 - 25 | RTS1 -> DCD1 -> CTS0 | | 1 | 24 - 06 - 56 | DTR1 -> DSR1 -> TCLKIN0 | | | 34 - 26 | DTECLK1 -> RCLKIN0 | | | 44 - 65 | HRS1 -> RI1 | +------+------------------+-------------------------------------+ | V.35 | +------+------------------+-------------------------------------+ | | 49 - 78 - 74 - 39| TXDA1 -> RXDA1 -> RXCA1 -> TXCA1 | | 1 | 14 - 35 - 55 - 16| TXDB1 -> RXDB1 -> RXCB1 -> TXCB1 | | | 63 - 45 - 25 | RTS1 -> DCD1 -> CTS1 | | | 24 - 06 | DTR1 -> DSR1 | +------+------------------+-------------------------------------+ +-----------------------------------------------------+ | Port 2 - Wrapped Signal Connections | +------+------------------+---------------------------+ | | Connector | | | Port | K9B Pins | Signals Wrapped | +------+------------------+---------------------------+ | RS-232-C | +------+------------------+---------------------------+ | | 66 - 28 | TXD2 -> RXD2 | | | 27 - 09 - 48 | RTS2 -> DCD2 -> CTS2 | | 2 | 47 - 68 - 70 | DTR2 -> DSR2 -> TCLKIN2 | | | 54 - 10 | DTECLK2 -> RCLKIN0 | | | 11 - 29 | HRS2 -> RI2 | +------+------------------+---------------------------+ | RS-422-A | +------+------------------+---------------------------+ | 2 | 13 - 33 | +TxD2 -> +RxD2 | | | 52 - 72 | -TxD2 -> -RxD2 | +------+------------------+---------------------------+ +-------------------------------------------------------+ | Port 3 - Wrapped Signal Connections | +------+------------------+-----------------------------+ | | Connector | | | Port | K9B Pins | Signals Wrapped | +------+------------------+-----------------------------+ | RS-232-C | +------+------------------+-----------------------------+ | | 69 - 39 | TXD3 -> RXD3 | | 3 | 30 - 12 - 51 - 32| RTS3 -> DCD3 -> CTS3 -> RI3 | | | 50 - 71 - 75 | DTR3 -> DSR3 -> TCLKIN3 | | | 73 - 17 | DTECLK3 -> RCLKIN3 | +------+------------------+-----------------------------+
Four optional female wrap plugs for the Selectable Cable are available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface boards, or the interface cable. Wrap plug P/N 40F9903 is used for RS-232-C operation on ports 0 through 3. Wrap plug P/N 53F3886 is used for RS-422-A operation on ports 0 and 2. Wrap plug P/N 40F9900 is used for V.35 operation on ports 0 and 1. Wrap plug P/N 40F9904 is used for X.21 operation on port 0.
The signals that are wrapped within the wrap plugs are shown in the following tables. The wrap connection is made from each transmit output signal to the corresponding receive input signal on the associated D-shell connector.
+-------------------------------------------------------+ | RS-232-C Wrap Connections for Ports 0 - 3 | +---------------------+---------------------------------+ | Associated Pins | Signals Wrapped | +---------------------+---------------------------------+ | 02 - 03 | TXD -> RXD | | 04 - 05 - 15 - 17 | RTS -> CTS -> TCLKIN -> RCLKIN | | 06 - 20 | DSR -> DTR | | 08 - 24 | DCD -> DTECLK | | 22 - 23 | RI -> HRS | +---------------------+---------------------------------+ +--------------------------------------------------------+ | RS-422-A Wrap Connections for Ports 0 and 2 | +---------------------+----------------------------------+ | Associated Pins | Signals Wrapped | +---------------------+----------------------------------+ | 02 - 03 - 23 - 22 | +TxD -> +RxD -> +TxCLK -> +RxCLK | | 04 - 05 - 24 - 17 | -TxD -> -RxD -> -TxCLK -> -RxCLK | +---------------------+----------------------------------+ +----------------------------------------------------+ | V.35 Wrap Connections for Ports 0 and 1 | +--------------------+-------------------------------+ | Associated Pins | Signals Wrapped | +--------------------+-------------------------------+ | 09 - 11 - 10 - 14 | TXDA -> RXDA -> TXCB -> RXCA | | 02 - 04 - 12 - 13 | TXDB -> RXDB -> TXCA -> RXCB | | 03 - 05 - 07 | RTS -> CTS -> DCD | | 06 - 15 | DSR -> DTR | +--------------------+-------------------------------+ +------------------------------------------+ | X.21 Wrap Connections for Port 0 | +------------------+-----------------------+ | Associated Pins | Signals Wrapped | +------------------+-----------------------+ | 02 - 04 | T(A) -> R(A) | | 03 - 05 - 06 | C(A) -> I(A) -> S(A) | | 09 - 11 | T(B) -> R(B) | | 10 - 12 - 13 | C(B) -> I(B) -> S(B) | +------------------+-----------------------+
An optional female wrap plug (P/N 40F9904) for the one-port X.21 cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the one-port X.21 cable.
The signals that are wrapped within the wrap plug are shown in the following table. The wrap connection is made from each transmit output signal to the corresponding receive input signal on the associated D-shell connector.
+------------------------------------------+ | X.21 Wrap Connections for Port 0 | +------------------+-----------------------+ | Associated Pins | Signals Wrapped | +------------------+-----------------------+ | 02 - 04 | T(A) -> R(A) | | 03 - 05 - 06 | C(A) -> I(A) -> S(A) | | 09 - 11 | T(B) -> R(B) | | 10 - 12 - 13 | C(B) -> I(B) -> S(B) | +------------------+-----------------------+
An optional female wrap plug (P/N 71F0163) for the one-port V.35 cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the one-port V.35 cable.
The signals that are wrapped within the wrap plug are shown in the following table. The wrap connection is made from each transmit output signal to the corresponding receive input signal on the associated D-shell connector.
+----------------------------------------------------+ | V.35 Wrap Connections for Port 0 | +--------------------+-------------------------------+ | Associated Pins | Signals Wrapped | +--------------------+-------------------------------+ | P - R - AA - V | TXDA -> RXDA -> TXCB -> RXCA | | S - T - Y - X | TXDB -> RXDB -> TXCA -> RXCB | | C - D - F | RTS -> CTS -> DCD | | E - H | DSR -> DTR | +--------------------+-------------------------------+
This chapter contains the following information for the Six-Port V.35 Interface Board/A and related external devices:
The Six-Port V.35 Interface Board/A contains the signal conditioning circuitry that converts TTL logic levels to the required logic levels (and vice versa) for up to six, synchronous serial ports. These ports are functionally compatible with the V.35 protocol.
The interface board connects to the co-processor adapter by a pair of 60-pin connectors and a 30-pin connector. Output signals exit the interface board through the 100-pin D-shell connector at the rear of the interface board.
Outbound transmit clocking and inbound transmit/receive clocking is supported for all ports of the six-port V.35 interface board.
The DTE/DCE clock select line is described under "Enables Register (ENREG)". This line is used as follows:
When operating as a DTE (clocks are supplied by an external device), the V.35 board provides the following data rates:
OR
Note:
For data rates above 512k bps, either port 0 or port 1 should be used.
The ID for this interface board is 18h.
The voltage requirements for this board are +5Vdc, +12Vdc, and -12Vdc.
Maximum lengths of external cabling from the V.35 interface board are:
The following tables provide the signal relationships between the DUSCC, the CIO, and the six serial ports (0 through 5). Input and output direction is given relative to the DUSCC and the CIO.
Note:
For diagnostic purposes, bits PC01 and PC11 of CIO-1, port C, are connected to the transmit clock receiver outputs as follows:
- Bit PC01 is connected to TXC0 IN
- Bit PC11 is connected ot TXC1 IN.
+-----------------------------------------------------------------+ | Signal Relationships | +------+------------+----------------+---------+------------+-----+ | Port | Signal | Signal Source/ | 100-Pin | 25-Pin | I/O | | | Name | Pin No. | Conn No.| Conn No. | | +------+------------+----------------+---------+------------+-----+ | 0 | TXD0 | DUSCC-0 / 39 | 94 | 02/TXDA | O | | | | | 70 | 14/TXDB | O | | | RXD0 | DUSCC-0 / 40 | 08 | 03/RXDA | I | | | | | 33 | 16/RXDB | I | | | TXC0 IN | DUSCC-0 / 44 | 76 | 15/TXCA IN | I | | | | | 52 | 12/TXCB IN | I | | | RXC0 | DUSCC-0 / 43 | 20 | 17/RXCA | I | | | | | 45 | 09/RXCB | I | | | TXC0 OUT | DUSCC-0 / 44 | 24 | 24/TXCA OUT| O | | | | | 49 | 11/TXCB OUT| O | | | RTS0 | DUSCC-0 / 45 | 42 | 04/RTS | O | | | CTS0 | DUSCC-0 / 35 | 15 | 05/CTS | I | | | DCD0 | DUSCC-0 / 42 | 89 | 08/DCD | I | | | DTR0 | CIO-0 / 37 | 18 | 20/DTR | O | | | DSR0 | CIO-0 / 10 | 66 | 06/DSR | I | | |DTE/DCE CLK0| ENREG / 19 | -- | -- | O | | | SG | --- | 34 | 07/SG | - | +------+------------+----------------+---------+------------+-----+ | 1 | TXD1 | DUSCC-0 / 15 | 21 | 02/TXDA | O | | | | | 46 | 14/TXDB | O | | | RXD1 | DUSCC-0 / 14 | 54 | 03/RXDA | I | | | | | 78 | 16/RXDB | I | | | TXC1 IN | DUSCC-0 / 10 | 06 | 15/TXCA IN | I | | | | | 31 | 12/TXCB IN | I | | | RXC1 | DUSCC-0 / 11 | 41 | 17/RXCA | I | | | | | 16 | 09/RXCB | I | | | TXC1 OUT | DUSCC-0 / 10 | 73 | 24/TXCA OUT| O | | | | | 97 | 11/TXCB OUT| O | | | RTS1 | DUSCC-0 / 09 | 43 | 04/RTS | O | | | CTS1 | DUSCC-0 / 19 | 65 | 05/CTS | I | | | DCD1 | DUSCC-0 / 12 | 40 | 08/DCD | I | | | DTR1 | CIO-0 / 36 | 91 | 20/DTR | O | | | DSR1 | CIO-0 / 11 | 90 | 06/DSR | I | | |DTE/DCE CLK1| ENREG / 18 | -- | -- | O | | | SG | --- | 17 | 07/SG | - | +------+------------+----------------+---------+------------+-----+ | 2 | TXD2 | DUSCC-1 / 39 | 47 | 02/TXDA | O | | | | | 22 | 14/TXDB | O | | | RXD2 | DUSCC-1 / 40 | 58 | 03/RXDA | I | | | | | 82 | 16/RXDB | I | | | TXC2 IN | DUSCC-1 / 44 | 77 | 15/TXCA IN | I | | | | | 53 | 12/TXCB IN | I | | | RXC2 | DUSCC-1 / 43 | 38 | 17/RXCA | I | | | | | 13 | 09/RXCB | I | | | TXC2 OUT | DUSCC-1 / 44 | 98 | 24/TXCA OUT| O | | | | | 74 | 11/TXCB OUT| O | | | RTS2 | DUSCC-1 / 45 | 92 | 04/RTS | O | | | CTS2 | DUSCC-1 / 35 | 86 | 05/CTS | I | | | DCD2 | DUSCC-1 / 42 | 62 | 08/DCD | I | | | DTR2 | CIO-0 / 35 | 69 | 20/DTR | O | | | DSR2 | CIO-0 / 12 | 88 | 06/DSR | I | | |DTE/DCE CLK2| ENREG / 17 | -- | -- | O | | | SG | --- | 63 | 07/SG | - | +------+------------+----------------+---------+------------+-----+ | 3 | TXD3 | DUSCC-1 / 15 | 71 | 02/TXDA | O | | | | | 95 | 14/TXDB | O | | | RXD3 | DUSCC-1 / 14 | 29 | 03/RXDA | I | | | | | 04 | 16/RXDB | I | | | TXC3 IN | DUSCC-1 / 10 | 56 | 15/TXCA IN | I | | | | | 80 | 12/TXCB IN | I | | | RXC3 | DUSCC-1 / 11 | 19 | 17/RXCA | I | | | | | 44 | 09/RXCB | I | | | TXC3 OUT | DUSCC-1 / 10 | 25 | 24/TXCA OUT| O | | | | | 50 | 11/TXCB OUT| O | | | RTS3 | DUSCC-1 / 09 | 93 | 04/RTS | O | | | CTS3 | DUSCC-1 / 19 | 87 | 05/CTS | I | | | DCD3 | DUSCC-1 / 12 | 61 | 08/DCD | I | | | DTR3 | CIO-0 / 34 | 68 | 20/DTR | O | | | DSR3 | CIO-0 / 13 | 64 | 06/DSR | I | | |DTE/DCE CLK3| ENREG / 16 | -- | -- | O | | | SG | --- | 67 | 07/SG | - | +------+------------+----------------+---------+------------+-----+ | 4 | TXD4 | DUSCC-2 / 39 | 72 | 02/TXDA | O | | | | | 96 | 14/TXDB | O | | | RXD4 | DUSCC-2 / 40 | 28 | 03/RXDA | I | | | | | 03 | 16/RXDB | I | | | TXC4 IN | DUSCC-2 / 44 | 27 | 15/TXCA IN | I | | | | | 02 | 12/TXCB IN | I | | | RXC4 | DUSCC-2 / 43 | 32 | 17/RXCA | I | | | | | 07 | 09/RXCB | I | | | TXC4 OUT | DUSCC-2 / 44 | 99 | 24/TXCA OUT| O | | | | | 75 | 11/TXCB OUT| O | | | RTS4 | DUSCC-2 / 45 | 37 | 04/RTS | O | | | CTS4 | DUSCC-2 / 35 | 59 | 05/CTS | I | | | DCD4 | DUSCC-2 / 42 | 35 | 08/DCD | I | | | DTR4 | CIO-0 / 33 | 14 | 20/DTR | O | | | DSR4 | CIO-0 / 14 | 60 | 06/DSR | I | | |DTE/DCE CLK4| ENREG / 15 | -- | -- | O | | | SG | --- | 01 | 07/SG | - | +------+------------+----------------+---------+------------+-----+ | 5 | TXD5 | DUSCC-2 / 15 | 23 | 02/TXDA | O | | | | | 48 | 14/TXDB | O | | | RXD5 | DUSCC-2 / 14 | 57 | 03/RXDA | I | | | | | 81 | 16/RXDB | I | | | TXC5 IN | DUSCC-2 / 10 | 55 | 15/TXCA IN | I | | | | | 79 | 12/TXCB IN | I | | | RXC5 | DUSCC-2 / 11 | 30 | 17/RXCA | I | | | | | 05 | 09/RXCB | I | | | TXC5 OUT | DUSCC-2 / 10 | 26 | 24/TXCA OUT| O | | | | | 51 | 11/TXCB OUT| O | | | RTS5 | DUSCC-2 / 09 | 39 | 04/RTS | O | | | CTS5 | DUSCC-2 / 19 | 09 | 05/CTS | I | | | DCD5 | DUSCC-2 / 12 | 84 | 08/DCD | I | | | DTR5 | CIO-0 / 32 | 12 | 20/DTR | O | | | DSR5 | CIO-0 / 15 | 85 | 06/DSR | I | | |DTE/DCE CLK5| ENREG / 14 | -- | -- | O | | | SG | --- | 83 | 07/SG | - | +------+------------+----------------+---------+------------+-----+
The 100-pin D-shell female connector on the Six-Port V.35 Interface Board/A is shown below.
26 \ / 01 51 \ / 27 75 \ / 52 100 \ / 76A typical 25-pin D-shell male connector on the Six-Port Cable is as follows.
01 \ / 13 14 \ / 25The pin assignments for the 100-pin connector on the Six-Port V.35 Interface Board/A and the corresponding pin assignments for the 25-pin connectors on the Six-Port V.35 Cable are listed in Table 33.. Table 33. Six-Port V.35 Connector Pin Assignments
+-----------+----+------------------------+-----------+ | Signal | I/O| 100-Pin Connector | 25-Pin | | Name | | Ports 0-5 | Connectors| | | | 0 1 2 3 4 5 | | +-----------+----+------------------------+-----------+ | TXDA | O | 94 21 47 71 72 23 | 02 | +-----------+----+------------------------+-----------+ | TXDB | O | 70 46 22 95 96 48 | 14 | +-----------+----+------------------------+-----------+ | RXDA | I | 08 54 58 29 28 57 | 03 | +-----------+----+------------------------+-----------+ | RXDB | I | 33 78 82 04 03 81 | 16 | +-----------+----+------------------------+-----------+ | TXCA IN | I | 76 06 77 56 27 55 | 15 | +-----------+----+------------------------+-----------+ | TXCB IN | I | 52 31 53 80 02 79 | 12 | +-----------+----+------------------------+-----------+ | RXCA | I | 20 41 38 19 32 30 | 17 | +-----------+----+------------------------+-----------+ | RXCB | I | 45 16 13 44 07 05 | 09 | +-----------+----+------------------------+-----------+ | TXCA OUT | O | 24 73 98 25 99 26 | 24 | +-----------+----+------------------------+-----------+ | TXCB OUT | O | 49 97 74 50 75 51 | 11 | +-----------+----+------------------------+-----------+ | RTS | O | 42 43 92 93 37 39 | 04 | +-----------+----+------------------------+-----------+ | CTS | I | 15 65 86 87 59 09 | 05 | +-----------+----+------------------------+-----------+ | DCD | I | 89 40 62 61 35 84 | 08 | +-----------+----+------------------------+-----------+ | DTR | O | 18 91 69 68 14 12 | 20 | +-----------+----+------------------------+-----------+ | DSR | I | 66 90 88 64 60 85 | 06 | +-----------+----+------------------------+-----------+ | SGND | -- | 34 17 63 67 01 83 | 07 | +-----------+----+------------------------+-----------+ | FGND | -- | 100 (Cable Shield) | 01 | +-----------+----+------------------------+-----------+
With All Ports Wrapped (100-Pin Wrap Plug)
A Six-Port V.35 Cable is available as an option to support the Six-Port V.35 Interface Board/A. The six-port cable converts the 100-pin female D-shell connector (K9B) on the co-processor adapter to appropriate connector interfaces for external cabling. This cable is 1.2 meters (4 feet) long. It has a 100-pin male D-shell connector (K9A) on one end that attaches to the connector on the co-processor adapter. At the other end of the cable is a molded distribution box, containing six, 25-pin, male, D-shell connectors (K00 - K05) that attach to external cabling.
The approximate dimensions of the distribution box are 200 mm (7.9 in.) long by 76 mm (3 in.) high, by 38 mm (1.5 in.) deep.
Six-Port V.35 Cable
+-----+ +-----+ +------------------+
| +-+ +-+ | | Port 0 (K00) |
| | | | | +------------+ |
|110-pin| |100-pin+-----------------------------+ \------------/ |
|female | |male +-----------------------------+ Port 1 (K01) |
|(K9B) | |(K9A) | Cable (1.2 m) | +------------+ |
| | | | | \------------/ |
| +-+ +-+ | | Port 2 (K02) |
+-----+ +-----+ | +------------+ |
Rear of | \------------/ |
Co-Processor | Port 3 (K03) |
Adapter | +------------+ |
| \------------/ |
| Port 4 (K04) |
+---------------------------+ | +------------+ |
1 \ . . . . . . . . . . . . . / 13 ------>| \------------/ |
14 \ . . . . . . . . . . . . / 25 | Port 5 (K05) |
+-----------------------+ | +------------+ |
25-Pin D-Shell Connectors | \------------/ |
(K00 - K05) +------------------+
The following table shows the connections from connector K9A to connectors K00 through K05.
+---------------------------------------------------------------+ | K9A to K00 through K05 Connections | +-----------++-----------++-----------++-----------++-----------+ |K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # | +-----------++-----------++-----------++-----------++-----------+ |01 K04-07||21 K01-02||41 K01-17||61 K03-08||81 K05-16| |02 K04-12||22 K02-14||42 K00-04||62 K02-08||82 K02-16| |03 K04-16||23 K05-02||43 K01-04||63 K02-07||83 K05-07| |04 K03-16||24 K00-24||44 K03-09||64 K03-06||84 K05-08| |05 K05-09||25 K03-24||45 K00-09||65 K01-05||85 K05-06| |06 K01-15||26 K05-24||46 K01-14||66 K00-06||86 K02-05| |07 K04-09||27 K04-15||47 K02-02||67 K03-07||87 K03-05| |08 K00-03||28 K04-03||48 K05-14||68 K03-20||88 K02-06| |09 K05-05||29 K03-03||49 K00-11||69 K02-20||89 K00-08| |10 Not used||30 K05-17||50 K03-11||70 K00-14||90 K01-06| |11 Not used||31 K01-12||51 K05-11||71 K03-02||91 K01-20| |12 K05-20||32 K04-17||52 K00-12||72 K04-02||92 K02-04| |13 K02-09||33 K00-16||53 K02-12||73 K01-24||93 K03-04| |14 K04-20||34 K00-07||54 K01-03||74 K02-11||94 K00-02| |15 K00-05||35 K04-08||55 K05-15||75 K04-11||95 K03-14| |16 K01-09||36 Not used||56 K03-15||76 K00-15||96 K04-14| |17 K01-07||37 K04-04||57 K05-03||77 K02-15||97 K01-11| |18 K00-20||38 K02-17||58 K02-03||78 K01-16||98 K02-24| |19 K03-17||39 K05-04||59 K04-05||79 K05-12||99 K04-24| |20 K00-17||40 K01-08||60 K04-06||80 K03-12||100 Shield| +-----------++-----------++-----------++-----------++-----------+
The 100-pin D-shell male connector on the Six-Port V.35 Cable is as follows..
01 \ / 26
27 \ / 51
52 \ / 75
76 \ / 100
A typical 25-pin D-shell male connector on the Six-Port V.35 Cable
is as follows.
01 \ / 13 14 \ / 25
The following cabling recommendations apply for all cables that are to be constructed for use with the co-processor adapter. Correct operation of any interface depends on several factors that should be taken into consideration during installation.
Typical physical characteristics for cables are listed below. Consult cable manufacturer catalogs for further information.
An optional diagnostic wrap plug is available with the Hardware Maintenance Library for diagnosing problems with the Six-Port V.35 Interface Board/A, as well as the co-processor adapter. This 100-pin male wrap plug (P/N 72F0168) is designed to wrap all signals at connector K9B. (No cable is associated with this wrap plug.)
The following tables show all board-wrapped signal connections for ports 0 through 5.
+-------------------------------------------------+ | Board-Wrapped Connections | +------+--------------+---------------------------+ | | Connector | | | Port | K9B Pins | Signals Wrapped | +------+--------------+---------------------------+ | | 94 - 08 - 76 | TXDA0 -> RXDA0 -> TXCA0 IN| | | 70 - 33 - 52 | TXDB0 -> RXDB0 -> TXCB0 IN| | +--------------+---------------------------+ | 0 | 24 - 20 | TXCA0 OUT -> RXCA0 | | | 49 - 45 | TXCB0 OUT -> RXCB0 | | +--------------+---------------------------+ | | 42 - 15 - 89 | RTS0 -> CTS0 -> DCD0 | | +--------------+---------------------------+ | | 18 - 66 | DTR0 -> DSR0 | +------+--------------+---------------------------+ | | 21 - 54 - 06 | TXDA1 -> RXDA1 -> TXCA1 IN| | | 46 - 78 - 31 | TXDB1 -> RXDB1 -> TXCB1 IN| | +--------------+---------------------------+ | 1 | 73 - 41 | TXCA1 OUT -> RXCA1 | | | 97 - 16 | TXCB1 OUT -> RXCB1 | | +--------------+---------------------------+ | | 43 - 65 - 40 | RTS1 -> CTS1 -> DCD1 | | +--------------+---------------------------+ | | 91 - 90 | DTR1 -> DSR1 | +------+--------------+---------------------------+ | | 47 - 58 - 77 | TXDA2 -> RXDA2 -> TXCA2 IN| | | 22 - 82 - 53 | TXDB2 -> RXDB2 -> TXCB2 IN| | +--------------+---------------------------+ | 2 | 98 - 38 | TXCA2 OUT -> RXCA2 | | | 74 - 13 | TXCB2 OUT -> RXCB2 | | +--------------+---------------------------+ | | 92 - 86 - 62 | RTS2 -> CTS2 -> DCD2 | | +--------------+---------------------------+ | | 69 - 88 | DTR2 -> DSR2 | +------+--------------+---------------------------+ | | 71 - 29 - 56 | TXDA3 -> RXDA3 -> TXCA3 IN| | | 95 - 04 - 80 | TXDB3 -> RXDB3 -> TXCB3 IN| | +--------------+---------------------------+ | 3 | 25 - 19 | TXCA3 OUT -> RXCA3 | | | 50 - 44 | TXCB3 OUT -> RXCB3 | | +--------------+---------------------------+ | | 93 - 87 - 61 | RTS3 -> CTS3 -> DCD3 | | +--------------+---------------------------+ | | 68 - 64 | DTR3 -> DSR3 | +------+--------------+---------------------------+ | | 72 - 28 - 27 | TXDA4 -> RXDA4 -> TXCA4 IN| | | 96 - 03 - 02 | TXDB4 -> RXDB4 -> TXCB4 IN| | +--------------+---------------------------+ | 4 | 99 - 32 | TXCA4 OUT -> RXCA4 | | | 75 - 07 | TXCB4 OUT -> RXCB4 | | +--------------+---------------------------+ | | 37 - 59 - 35 | RTS4 -> CTS4 -> DCD4 | | +--------------+---------------------------+ | | 14 - 60 | DTR4 -> DSR4 | +------+--------------+---------------------------+ | | 23 - 57 - 55 | TXDA5 -> RXDA5 -> TXCA5 IN| | | 48 - 81 - 79 | TXDB5 -> RXDB5 -> TXCB5 IN| | +--------------+---------------------------+ | 5 | 26 - 30 | TXCA5 OUT -> RXCA5 | | | 51 - 05 | TXCB5 OUT -> RXCB5 | | +--------------+---------------------------+ | | 39 - 09 - 84 | RTS5 -> CTS5 -> DCD5 | | +--------------+---------------------------+ | | 12 - 85 | DTR5 -> DSR5 | +------+--------------+---------------------------+
An optional wrap plug for the Six-Port V.35 Cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the interface cable. This 25-pin female wrap plug (P/N 72F0167) is used for V.35 operation on all six ports.
The signals that are wrapped within the 25-pin wrap plug are shown in the following table.
+-------------------------------------------------------+ | Cable-Wrapped Connections for Ports 0-5 | +---------------------+---------------------------------+ | Connectors | | | K00 to K05 | Signals Wrapped | +---------------------+---------------------------------+ | 02 - 03 - 15 | TXDA -> RXDA -> TXCA IN | | 14 - 16 - 12 | TXDB -> RXDB -> TXCB IN | +---------------------+---------------------------------+ | 24 - 17 | TXCA OUT -> RXCA | | 11 - 09 | TXCB OUT -> RXCB | +---------------------+---------------------------------+ | 04 - 05 - 08 | RTS -> CTS -> DCD | +---------------------+---------------------------------+ | 20 - 06 | DTR -> DSR | +---------------------+---------------------------------+
This chapter contains the following information for the Six-Port X.21 Interface Board/A and related external devices:
The Six-Port X.21 Interface Board/A contains the signal conditioning circuitry that converts TTL logic levels to the required logic levels (and vice versa) for six synchronous serial X.21 ports. Protocols for these electrical signals are user-programmable.
The interface board connects to the co-processor adapter by a pair of 60-pin connectors and a 30-pin connector. Output signals exit the interface board through the 78-pin D-shell connector at the rear of the interface board.
Outbound transmit and inbound receive clocking is supported for all ports of the six-port X.21 interface board.
The DTE/DCE clock select line is described under "Enables Register (ENREG)". This line is used as follows:
When operating as a DTE (clocks are supplied by an external device), the X.21 board provides the following data rates:
OR
Note:
For data rates above 512K bps, either port 0 or port 1 should be used.
The ID for this interface board is 28h.
The voltage requirement for this board is +5Vdc.
Maximum lengths of external cabling from the X.21 interface board are:
An optional IBM surge protection adapter can be used to provide voltage suppression circuitry for each port. See "Surge Protection Adapter".
The interface board ROS for the co-processor adapter is described fully in Chapter 3. "Electrical Interfaces". These tables also apply to the X.21 interface board.
The six-port X.21 interface board supports
X.21 operation on all ports. The
ROS field names for the X.21 signals are listed in Figure 32.,
along with the field names for the corresponding RS-232/RS-422 signals.
Figure 32. ROS Field Names
+---------------+-----------------+ | X.21 | RS-232/RS-422 | +---------------+-----------------+ | CONTROL | RTS | | INDICATE | CTS | | TX_EN | TXBLK | | X21_EN | DTR | | X21S0 | DSR | | X21S1 | DCD | +---------------+-----------------+
Interface Signal X.21 Name ------ --------- TxD T (transmit) RxD R (receive) -RTS C (control) -CTS I (indication) RxCLK S (signal element timing) TxCLK X (DTE signal element timing)
Realtime Control Microcode X.21 Name Logical Control Line Services Name ---------- ---------------------------------- -TxEN TXBLK -X21EN DTR -X21S1 DCD -X21S0 DSR
+-------+-------+---------------------------------------------+ |-X21S1 |-X21S0 | Status | +-------+-------+---------------------------------------------+ | 0 | 0 | At least 16 bits of 0s were detected, | | | | (I=off,-X21EN=true). | | 1 | 1 | At least 16 bits of 1s were detected, | | | | (I=off,-X21EN=true). | | 1 | 0 | At least 16 bits of alternating 0s and 1s | | | | (that is, 010101..) were detected, | | | | (I=off, -X21EN=true). | | 0 | 1 | Reset state (-X21EN=false). | +-------+-------+---------------------------------------------+
For proper operation, the pattern recognition hardware should be reset prior to any communications. The sample code shown in Figure 34. accomplishes this reset. This code assumes -X21EN is in the disabled state. A pull-up resistor assures the disabled state, until the CIO bits are enabled. This routine resets the hardware, even if there is no external clock.
The code functions as follows.
;------ DUSCC EQUATES FOR PROM SERVICES CALL
CTPRH EQU 08H ;COUNTER PRESET HIGH REGISTER
CTPRL EQU 09H ;COUNTER PRESET LOW REGISTER
CTCR EQU 0AH ;COUNTER CONTROL REGISTER
PCR EQU 0EH ;PIN CONFIGURATION REGISTER
CCR EQU 0FH ;CHANNEL COMMAND REGISTER
;------ DUSCC INIT TABLE FOR X.21 RESET
X21_RST_TBL DB 8 ;8 REGS TO WRITE
DB PCR,23H ;RTXC=IN , TRXC=COUNTER OUTPUT
DB CTPRH,00H ;PRESET HIGH
DB CTPRL,02H ;PRESET LOW
DB CTCR,22H ;PULSE OUTPUT, CLOCK SOURCE = X1/CLK
DB CCR,83H ;LOAD PRESET VALUE TO COUNTER
DB CCR,80H ;START COUNTER TO RESET X.21 PAL
DB CCR,81H ;STOP COUNTER
DB PCR,20H ;PUT RTXC AND TRXC BACK TO INPUT MODE
;------ CODE START HERE
;------ INIT X.21 PORT 0
MOV DX,800H ;
IN AL,DX ;
AND AL,11111110B ;SELECT DTE CLOCK FOR PORT 0
OUT DX,AL ;
LEA SI,X21_RST_TBL ;GET TABLE POINTER
MOV AX,0 ;AH=0, AL=PORT#. PREPARE TO INIT PORT 0
INT 0A4H ;CALL PROM SERVICES TO INIT DUSCC FROM TABLE
MOV DX,800H ;
IN AL,DX ;
OR AL,00000001B ;SELECT DCE CLOCK FOR PORT 0
OUT DX,AL ;
;------ INIT X.21 PORT 1
MOV DX,800H ;
IN AL,DX ;
AND AL,11111101B ;SELECT DTE CLOCK FOR PORT 1
OUT DX,AL ;
LEA SI,X21_RST_TBL ;GET TABLE POINTER
MOV AX,1 ;AH=0, AL=PORT#. PREPARE TO INIT PORT 1
INT 0A4H ;CALL PROM SERVICES TO INIT DUSCC FROM TABLE
MOV DX,800H ;
IN AL,DX ;
OR AL,00000010B ;SELECT DCE CLOCK FOR PORT 1
OUT DX,AL ;
The following tables provide the signal relationships between the DUSCC, the CIO, and the serial ports. Input and output direction is given relative to the DUSCC and the CIO.
+--------------------------------------------------------------+ | Signal Relationships | +------+------------+----------------+---------+---------+-----+ | Port | Signal | Signal Source/ | 78-Pin | 25-Pin | I/O | | | Name | Pin No. | Conn No.| Conn No.| | +------+------------+----------------+---------+---------+-----+ | 0 | T0 | DUSCC-0 / 39 | 40 | 02/T0A | O | | | | | 41 | 24/T0B | O | | | R0 | DUSCC-0 / 40 | 02 | 03/R0A | I | | | | | 62 | 17/R0B | I | | | C0 | DUSCC-0 / 45 | 01 | 04/C0A | O | | | | | 60 | 20/C0B | O | | | I0 | DUSCC-0 / 35 | 61 | 05/I0A | I | | | | | 42 | 06/I0B | I | | | X0 | DUSCC-0 / 44 | 22 | 08/X0A | I | | | | | 03 | 22/X0B | I | | | S0 | DUSCC-0 / 43 | 23 | 15/S0A | I | | | | | 21 | 23/S0B | I | | | SG | --- | 43 | 07/SG | - | | | -TxEN0 | CIO-0 / 37 | | | O | | | -X21EN0 | CIO-0 / 35 | | | O | | | -X21S1P0 | CIO-0 / 11 | | | I | | | -X21S0P0 | CIO-0 / 10 | | | I | +------+------------+----------------+---------+---------+-----+ | 1 | T1 | DUSCC-0 / 15 | 04 | 02/T1A | O | | | | | 05 | 24/T1B | O | | | R1 | DUSCC-0 / 14 | 64 | 03/R1A | I | | | | | 26 | 17/R1B | I | | | C1 | DUSCC-0 / 09 | 63 | 04/C1A | O | | | | | 24 | 20/C1B | O | | | I1 | DUSCC-0 / 19 | 25 | 05/I1A | I | | | | | 06 | 06/I1B | I | | | X1 | DUSCC-0 / 10 | 45 | 08/X1A | I | | | | | 65 | 22/X1B | I | | | S1 | DUSCC-0 / 11 | 46 | 15/S1A | I | | | | | 44 | 23/S1B | I | | | SG | --- | 07 | 07/SG | - | | | -TxEN1 | CIO-0 / 36 | | | O | | | -X21EN1 | CIO-0 / 34 | | | O | | | -X21S1P1 | CIO-1 / 36 | | | I | | | -X21S0P1 | CIO-1 / 37 | | | I | +------+------------+----------------+---------+---------+-----+ | 2 | T2 | DUSCC-1 / 39 | 66 | 02/T2A | O | | | | | 19 | 24/T2B | O | | | R2 | DUSCC-1 / 40 | 28 | 03/R2A | I | | | | | 57 | 17/R2B | I | | | C2 | DUSCC-1 / 45 | 27 | 04/C2A | O | | | | | 47 | 20/C2B | O | | | I2 | DUSCC-1 / 35 | 48 | 05/I2A | I | | | | | 68 | 06/I2B | I | | | X2 | DUSCC-1 / 44 | 09 | 08/X2A | I | | | | | 29 | 22/X2B | I | | | S2 | DUSCC-1 / 43 | 78 | 15/S2A | I | | | | | 76 | 23/S2B | I | | | SG | --- | 08 | 07/SG | - | | | -TxEN2 | CIO-0 / 33 | | | O | | | -X21EN2 | CIO-0 / 31 | | | O | | | -X21S1P2 | CIO-1 / 13 | | | I | | | -X21S0P2 | CIO-1 / 12 | | | I | +------+------------+----------------+---------+---------+-----+ | 3 | T3 | DUSCC-1 / 15 | 69 | 02/T3A | O | | | | | 20 | 24/T3B | O | | | R3 | DUSCC-1 / 14 | 31 | 03/R3A | I | | | | | 77 | 17/R3B | I | | | C3 | DUSCC-1 / 09 | 30 | 04/C3A | O | | | | | 50 | 20/C3B | O | | | I3 | DUSCC-1 / 19 | 51 | 05/I3A | I | | | | | 71 | 06/I3B | I | | | X3 | DUSCC-1 / 10 | 12 | 08/X3A | I | | | | | 32 | 22/X3B | I | | | S3 | DUSCC-1 / 11 | 59 | 15/S3A | I | | | | | 37 | 23/S3B | I | | | SG | --- | 67 | 07/SG | - | | | -TxEN3 | CIO-0 / 32 | | | O | | | -X21EN3 | CIO-0 / 30 | | | O | | | -X21S1P3 | CIO-1 / 34 | | | I | | | -X21S0P3 | CIO-1 / 35 | | | I | +------+------------+----------------+---------+---------+-----+ | 4 | T4 | DUSCC-2 / 39 | 73 | 02T4A | O | | | | | 10 | 24T4B | O | | | R4 | DUSCC-2 / 40 | 54 | 03R4A | I | | | | | 18 | 17R4B | I | | | C4 | DUSCC-2 / 45 | 34 | 04C4A | O | | | | | 35 | 20C4B | O | | | I4 | DUSCC-2 / 35 | 15 | 05I4A | I | | | | | 72 | 06I4B | I | | | X4 | DUSCC-2 / 44 | 74 | 08X4A | I | | | | | 49 | 22X4B | I | | | S4 | DUSCC-2 / 43 | 39 | 15S4A | I | | | | | 38 | 23S4B | I | | | SG | --- | 11 | 07SG | - | | | -TxEN4 | CIO-0 / 10 | | | O | | | -X21EN4 | CIO-0 / 12 | | | O | | | -X21S1P4 | CIO-1 / 15 | | | I | | | -X21S0P4 | CIO-1 / 14 | | | I | +------+------------+----------------+---------+---------+-----+ | 5 | T5 | DUSCC-2 / 15 | 55 | 02T5A | O | | | | | 13 | 24T5B | O | | | R5 | DUSCC-2 / 14 | 75 | 03R5A | I | | | | | 53 | 17R5B | I | | | C5 | DUSCC-2 / 09 | 16 | 04C5A | O | | | | | 17 | 20C5B | O | | | I5 | DUSCC-2 / 19 | 36 | 05I5A | I | | | | | 33 | 06I5B | I | | | X5 | DUSCC-2 / 10 | 56 | 08X5A | I | | | | | 52 | 22X5B | I | | | S5 | DUSCC-2 / 11 | 14 | 15S5A | I | | | | | 58 | 23S5B | I | | | SG | --- | 70 | 07SG | - | | | -TxEN5 | CIO-0 / 11 | | | O | | | -X21EN5 | CIO-0 / 13 | | | O | | | -X21S1P5 | CIO-1 / 32 | | | I | | | -X21S0P5 | CIO-1 / 33 | | | I | +------+------------+----------------+---------+---------+-----+
The 78-pin D-shell female connector on the Six-Port X.21 Interface Board/A is as follows.
20 \ / 01
39 \ / 21
59 \ / 40
78 \ / 60
A typical 25-pin D-shell male connector on the Six-Port Cable
is as follows.
01 \ / 13 14 \ / 25The pin assignments for the 78-pin connector on the Six-Port X.21 Interface Board/A and the corresponding pin assignments for the 25-pin connectors on the Six-Port X.21 Cable are listed in Table 34..
Table 34. Six-Port X.21 Connector Pin Assignments
+-----------+----+------------------------+-----------+ | Signal | I/O| 78-Pin Connector | 25-Pin | | Name | | Ports 0-5 | Connectors| | | | 0 1 2 3 4 5 | | +-----------+----+------------------------+-----------+ | T(A) | O | 40 04 66 69 73 55 | 02 | +-----------+----+------------------------+-----------+ | T(B) | O | 41 05 19 20 10 13 | 24 | +-----------+----+------------------------+-----------+ | R(A) | I | 02 64 28 31 54 75 | 03 | +-----------+----+------------------------+-----------+ | R(B) | I | 62 26 57 77 18 53 | 17 | +-----------+----+------------------------+-----------+ | C(A) | O | 01 63 27 30 34 16 | 04 | +-----------+----+------------------------+-----------+ | C(B) | O | 60 24 47 50 35 17 | 20 | +-----------+----+------------------------+-----------+ | I(A) | I | 61 25 48 51 15 36 | 05 | +-----------+----+------------------------+-----------+ | I(B) | I | 42 06 68 71 72 33 | 06 | +-----------+----+------------------------+-----------+ | X(A) | O | 22 45 09 12 74 56 | 08 | +-----------+----+------------------------+-----------+ | X(B) | O | 03 65 29 32 49 52 | 22 | +-----------+----+------------------------+-----------+ | S(A) | I | 23 46 78 59 39 14 | 15 | +-----------+----+------------------------+-----------+ | S(B) | I | 21 44 76 37 38 58 | 23 | +-----------+----+------------------------+-----------+ | SG | -- | 43 07 08 67 11 70 | 07 | | | - | | | +-----------+----+------------------------+-----------+
(Six-Port X.21 Interface Board/A Only)
With All Ports Wrapped
A Six-Port X.21 Cable is available as an option to support the Six-Port X.21 Interface Board/A. The six-port cable converts the 78-pin female D-shell connector (K9B) on the co-processor adapter to appropriate connector interfaces for external cabling. This cable is 1.8 meters (6 feet) long. It has a 78-pin male D-shell connector (K9A) on one end that attaches to the connector on the co-processor adapter. At the other end of the cable is a molded distribution box, containing six, 25-pin, male, D-shell connectors (K00 - K05) that attach to external cabling.
The approximate dimensions of the distribution box are 200 mm (7.9 in.) long by 76 mm (3 in.) high, by 38 mm (1.5 in.) deep.
Six-Port X.21 Cable
+-----+ +-----+ +------------------+
| +-+ +-+ | | Port 0 (K00) |
| | | | | +------------+ |
|78-pin | |78-pin +-----------------------------+ \------------/ |
|female | |male +-----------------------------+ Port 1 (K01) |
|(K9B) | |(K9A) | Cable (1.8 m) | +------------+ |
| | | | | \------------/ |
| +-+ +-+ | | Port 2 (K02) |
+-----+ +-----+ | +------------+ |
Rear of | \------------/ |
Co-Processor | Port 3 (K03) |
Adapter | +------------+ |
| \------------/ |
| Port 4 (K04) |
+---------------------------+ | +------------+ |
1 \ . . . . . . . . . . . . . / 13 ------>| \------------/ |
14 \ . . . . . . . . . . . . / 25 | Port 5 (K05) |
+-----------------------+ | +------------+ |
25-Pin D-Shell Connectors | \------------/ |
(K00 - K05) +------------------+
The following table shows the connections from connector K9A to connectors K00 through K05.
+---------------------------------------------------------------+ | K9A to K00 through K05 Connections | +-----------++-----------++-----------++-----------++-----------+ |K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # ||K9A Pin # | +-----------++-----------++-----------++-----------++-----------+ |01 K00-04||17 K05-20||33 K05-06||49 K04-22||65 K01-22| |02 K00-03||18 K04-17||34 K04-04||50 K03-20||66 K02-02| |03 K00-22||19 K02-24||35 K04-20||51 K03-05||67 K03-07| |04 K01-02||20 K03-24||36 K05-05||52 K05-22||68 K02-06| |05 K01-24||21 K00-23||37 K03-23||53 K05-17||69 K03-02| |06 K01-06||22 K00-08||38 K04-23||54 K04-03||70 K05-07| |07 K01-07||23 K00-15||39 K04-15||55 K05-02||71 K03-06| |08 K02-07||24 K01-20||40 K00-02||56 K05-08||72 K04-06| |09 K02-08||25 K01-05||41 K00-24||57 K02-17||73 K04-02| |10 K04-24||26 K01-17||42 K00-06||58 K05-23||74 K04-08| |11 K04-07||27 K02-04||43 K00-07||59 K03-15||75 K05-03| |12 K03-08||28 K02-03||44 K01-23||60 K00-20||76 K02-23| |13 K05-24||29 K02-22||45 K01-08||61 K00-05||77 K03-17| |14 K05-15||30 K03-04||46 K01-15||62 K00-17||78 K02-15| |15 K04-05||31 K03-03||47 K02-20||63 K01-04|| | |16 K05-04||32 K03-22||48 K02-05||64 K01-03|| | +-----------++-----------++-----------++-----------++-----------+
The 78-pin D-shell male connector on the Six-Port X.21 Cable is as follows.
01 \ / 20
21 \ / 39
40 \ / 59
60 \ / 78
A typical 25-pin D-shell male connector on the Six-Port X.21 Cable
is as follows.
01 \ / 13 14 \ / 25
The following cabling recommendations apply for all cables that are to be constructed for use with the co-processor adapter. Correct operation of any interface depends on several factors that should be taken into consideration during installation.
Typical physical characteristics for cables are listed below. Consult cable manufacturer catalogs for further information.
An optional IBM surge protection adapter can be used to provide voltage suppression circuitry in conjunction with the Six-Port X.21 Interface Board/A and the Six-Port X.21 Cable for each port where voltage suppression is desired. This adapter has two 25-pin D-shell connectors, which interconnect the appropriate interface cable connector to the cabling.
An optional wrap plug is available with the Hardware Maintenance Library for diagnosing problems with the Six-Port X.21 Interface Board/A, as well as the co-processor adapter. This 78-pin male wrap plug (P/N 85F0205) is designed to wrap all signals used for X.21 operation at connector K9B. (No cable is associated with this wrap plug.)
The following table shows all board-wrapped signal connections for ports 0 through 5.
+------------------------------------------------+ | Board-Wrapped Connections for Ports 0-5 | +----+-------------------+-----------------------+ | | Connector | | |Port| K9B Pins | Signals Wrapped | +----+-------------------+-----------------------+ | | 40 - 02 | T0(A) - R0(A) | | | 41 - 62 | T0(B) - R0(B) | | 0 | 01 - 61 | C0(A) - I0(A) | | | 60 - 42 | C0(B) - I0(B) | | | 22 - 23 | X0(A) - S0(A) | | | 03 - 21 | X0(B) - S0(B) | +----+-------------------+-----------------------+ | | 04 - 64 | T1(A) - R1(A) | | | 05 - 26 | T1(B) - R1(B) | | 1 | 63 - 25 | C1(A) - I1(A) | | | 24 - 06 | C1(B) - I1(B) | | | 45 - 46 | X1(A) - S1(A) | | | 65 - 44 | X1(B) - S1(B) | +----+-------------------+-----------------------+ | | 66 - 28 | T2(A) - R2(A) | | | 19 - 57 | T2(B) - R2(B) | | 2 | 27 - 48 | C2(A) - I2(A) | | | 47 - 68 | C2(B) - I2(B) | | | 09 - 78 | X2(A) - S2(A) | | | 29 - 76 | X2(B) - S2(B) | +----+-------------------+-----------------------+ | | 69 - 31 | T3(A) - R3(A) | | | 20 - 77 | T3(B) - R3(B) | | 3 | 30 - 51 | C3(A) - I3(A) | | | 50 - 71 | C3(B) - I3(B) | | | 12 - 59 | X3(A) - S3(A) | | | 32 - 37 | X3(B) - S3(B) | +----+-------------------+-----------------------+ | | 73 - 54 | T4(A) - R4(A) | | | 10 - 18 | T4(B) - R4(B) | | 4 | 34 - 15 | C4(A) - I4(A) | | | 35 - 72 | C4(B) - I4(B) | | | 74 - 39 | X4(A) - S4(A) | | | 49 - 38 | X4(B) - S4(B) | +----+-------------------+----------------------+ | | 55 - 75 | T5(A) - R5(A) | | | 13 - 53 | T5(B) - R5(B) | | 5 | 16 - 36 | C5(A) - I5(A) | | | 17 - 33 | C5(B) - I5(B) | | | 56 - 14 | X5(A) - S5(A) | | | 52 - 58 | X5(B) - S5(B) | +----+-------------------+-----------------------+
An optional diagnostic wrap plug for the Six-Port X.21 Cable is available with the Hardware Maintenance Library to aid in diagnosing problems with the co-processor adapter, the interface board, or the interface cable. This 25-pin female wrap plug (P/N 85F0206) is used for X.21 operation on all ports.
The signals that are wrapped within the 25-pin wrap plug are shown here. The wrap connection is made from each transmit output signal and looped back to the corresponding receive input signal on the 25-pin D-shell connector.
+----------------------------------------+ | Cable Wrap Connections for Ports 0-5 | +-----------------+----------------------+ | Connectors | | | K00 to K05 | Signals Wrapped | +-----------------+----------------------+ | 02 -> 03 | T(A) -> R(A) | | 24 -> 17 | T(B) -> R(B) | | 04 -> 05 | C(A) -> I(A) | | 20 -> 06 | C(B) -> I(B) | | 08 -> 15 | X(A) -> S(A) | | 22 -> 23 | X(B) -> S(B) | +-----------------+----------------------+
This section describes in detail the registers contained within the RAM controller and bus master interface chip.
All registers are byte read and write, unless otherwise noted. All unused addresses should be considered as reserved. Bits are described with bit 0 being the least significant bit.
Both power-up reset and command reset values are shown in the "reset condition" section of each register. In these sections, bits shown with "U" represent an undefined or unpredictable state after power-up or reset commands. Bits which are designated with "S" remain in the same state as before the reset command.
See "Bus Master Micro Channel Interface".
This 8-bit, read/write register is used to reset the internal bus master registers and control logic to a known state. During normal operation it is not necessary to use this register.
I/O Addresses
-------------
Co-Processor Adapter
BMCH1 = 00A0h, 8-bit R/W
System Unit = None
MSB LSB
Bit 7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| X | X | X | X | X | X | X |DIS|
+---+---+---+---+---+---+---+---+
Bits 1-7, Reserved
These bits are always read as 0s.
Bit 0, DIS
When this bit equals 1, it resets the CH1 internal registers and control
logic, and holds the channel in this reset state.
When this bit equals 0, it releases
the channel from the reset state for further operation.
This 16-bit read/write register is used to identify the co-processor adapter card to the system. This register can also be read by the POS registers. The low-order byte of CRDIDREG is mapped into POS 0, and the high-order byte is mapped into POS 1.
I/O Addresses
-------------
Co-Processor Adapter
CRDIDREG = 0088h, 16-bit R/W
System Unit = None
+---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--+
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
+-+-+-+-+-+-+-+-+-+-+-+-++-++-++-++-++-++-++-++-++-++-+
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +-- ID0
| | | | | | | | | | | | | | +----- ID1
| | | | | | | | | | | | | +-------- ID2
| | | | | | | | | | | | +----------- ID3
| | | | | | | | | | | +-------------- ID4
| | | | | | | | | | +----------------- ID5
| | | | | | | | | +-------------------- ID6
| | | | | | | | +----------------------- ID7
| | | | | | | +-------------------------- ID8
| | | | | | +----------------------------- ID9
| | | | | +-------------------------------- ID10
| | | | +------------------------------------ ID11
| | | +---------------------------------------- ID12
| | +-------------------------------------------- ID13
| +------------------------------------------------ ID14
+---------------------------------------------------- ID15
Bits 0-15, Card ID
These bits identify the card as a co-processor adapter.
Bits 0-7 are programmed by ROS to read 70h,
and bits 8-15 are programmed by ROS to read 8Fh for the
co-processor adapter card.
Power-up: 0000 0000 0000 0000
Reset command: SSSS SSSS SSSS SSSS
The CPUPG is a read/write register that is accessible by the system unit's CPU (processor) or the co-processor adapter's processor. This register determines which page of RAM is viewable by the system unit. It is activated automatically on any valid system unit access to the co-processor adapter RAM, assuming the RAM has been properly gated onto the bus, and that the DMAPG enable bit in POS5 and INITREG1 is reset. If the DMAPG enable bit is set, a valid system unit access uses the arbitration level bits to access an entry in the DMAPG register. For a 2M-byte window, the CPU page is never activated. In this case, the system unit has complete linear addressability of the card's memory. Also, in cases where the window size is equal to the size of the installed memory, the system unit has complete linear addressability of the card's memory, and the CPU page is not activated.
I/O Addresses
-------------
Co-Processor Adapter
CPUPG = 0014h or 005Eh
System Unit
CPUPG = Base + 0005h
+--+--+--+--+--+--+--+--+ Window Size
|D7|D6|D5|D4|D3|D2|D1|D0| +------------------------------------------+
+-++-++-++-++-++-++-++-++ |8KB 16KB 32KB 64KB 128KB 512KB 1MB 2MB|
| | | | | | | | +------------------------------------------+
| | | | | | | +--- A13 A14 A15 A16 A17 A19 A20 0
| | | | | | +------ A14 A15 A16 A17 A18 A20 0 0
| | | | | +--------- A15 A16 A17 A18 A19 0 0 0
| | | | +------------ A16 A17 A18 A19 A20 0 0 0
| | | +--------------- A17 A18 A19 A20 0 0 0 0
| | +------------------ A18 A19 A20 0 0 0 0 0
| +--------------------- A19 A20 0 0 0 0 0 0
+------------------------ A20 0 0 0 0 0 0 0
Bits 0-7, Page Values
A page value (0-FFh) determines where in the co-processor adapter's
memory the system unit can view. To calculate the
absolute RAM location addressed within the co-processor adapter's
memory map (not the absolute RAM location within the
system unit memory), the page value may be thought of
as providing address lines to the RAM.
The number of address lines provided is dependent on the window size.
The user should be aware that if
a simultaneous write by the system unit and the co-processor adapter occurs,
the value of the register is uncertain.
The first write to this register by either the
system unit or the co-processor adapter activates the RAM on the system unit side
if it was previously deactivated by either a
power-up or channel reset. RAM is never
activated before the system unit refresh activity is detected,
or if the sleep bit is active.
Note:
A dynamic change of the window size makes a corresponding change to the CPU page value. For example, if the window size is set at 8KB and the CPU page value is 08h, dynamically changing the window size to 16KB results in a CPU page value of 04h.
Power-up: UUUU UUUU
Reset command: SSSS SSSS
The DMA page registers are read/write registers that are accessible by the system unit's microprocessor, the co-processor adapter's microprocessor, or alternate system unit bus masters. The registers operate similar to the CPU page register, except that they determine which page of RAM may be viewed by an alternate bus master, or the system unit microprocessor if the DMAPG enable bit is set. The correct DMA page register is automatically activated on any valid system unit access to co-processor adapter memory, based on the ARB level present on the bus during the access. For a 2MB window, the DMA page registers are never activated. In this case, the system unit has complete linear addressability of the card's memory. Also in cases where the window size is equal to the size of the installed memory, the system unit has complete linear addressability of the card's memory, and the CPU page is not activated.
ARB level F activates the present CPUPG. Any other ARB level on the bus points to the appropriate DMAPG. Hence, all 16 possible system unit bus masters can have a separate page or window into the co-processor adapter's memory. Also it is possible for an alternate master to update its DMAPG. The master performs an I/O to offset 05h, and the ARB level present on the bus during this cycle points to the correct DMAPG to be updated. This gives any system unit bus master the ability to completely page through the co-processor adapter's memory. All of this is possible assuming the co-processor adapter memory has been properly gated onto the Micro Channel bus by the device driver.
+--+--+--+--+--+--+--+--+ Window Size |D7|D6|D5|D4|D3|D2|D1|D0| +------------------------------------------+ +-++-++-++-++-++-++-++-++ |8KB 16KB 32KB 64KB 128KB 512KB 1MB 2MB| | | | | | | | | +------------------------------------------+ | | | | | | | +--- A13 A14 A15 A16 A17 A19 A20 0 | | | | | | +------ A14 A15 A16 A17 A18 A20 0 0 | | | | | +--------- A15 A16 A17 A18 A19 0 0 0 | | | | +------------ A16 A17 A18 A19 A20 0 0 0 | | | +--------------- A17 A18 A19 A20 0 0 0 0 | | +------------------ A18 A19 A20 0 0 0 0 0 | +--------------------- A19 A20 0 0 0 0 0 0 +------------------------ A20 0 0 0 0 0 0 0
+----------+--------------+---------------+----------------------+ | | System Unit | Co-Processor | Alternate Master | | Register | I/O Address | I/O Address | System Unit Address | +----------+--------------+---------------+----------------------+ | DMAPG0 | (20) | 40 | Base+05h & ARB 0 | | DMAPG1 | (22) | 42 | Base+05h & ARB 1 | | DMAPG2 | (24) | 44 | Base+05h & ARB 2 | | DMAPG3 | (26) | 46 | Base+05h & ARB 3 | | DMAPG4 | (28) | 48 | Base+05h & ARB 4 | | DMAPG5 | (2A) | 4A | Base+05h & ARB 5 | | DMAPG6 | (2C) | 4C | Base+05h & ARB 6 | | DMAPG7 | (2E) | 4E | Base+05h & ARB 7 | | DMAPG8 | (30) | 50 | Base+05h & ARB 8 | | DMAPG9 | (32) | 52 | Base+05h & ARB 9 | | DMAPG10 | (34) | 54 | Base+05h & ARB A | | DMAPG11 | (36) | 56 | Base+05h & ARB B | | DMAPG12 | (38) | 58 | Base+05h & ARB C | | DMAPG13 | (3A) | 5A | Base+05h & ARB D | | DMAPG14 | (3C) | 5C | Base+05h & ARB E | | CPUPG | Base+05h | 14 | Base+05h & ARB F | | | or (3E) | or 5E | | +----------+--------------+---------------+----------------------+
Bits 0-7, Page Values
A page value (0-FFh) determines where in the co-processor adapter
memory that the alternate bus master may view. To calculate the
absolute RAM location addressed within the co-processor adapter's
memory map (not the absolute RAM location within the
system unit memory), the page value can be thought of
as providing address lines to the RAM.
The number of address lines provided is dependent on the window size.
The user should be aware that if
a simultaneous write to the register by the system unit and co-processor adapter occurs,
the value of the register is uncertain. RAM is never
activated before the system unit refresh activity is detected,
or if the sleep bit is active.
Power-up: UUUU UUUU
Reset command: SSSS SSSS
This register allows either the system unit or the co-processor adapter to determine which gate array is being used as the channel interface; it is a read-only register.
I/O Addresses
-------------
Co-Processor Adapter
GAID = 0018h
System Unit
PTRREG = 000Fh
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++
| | | | | | | | RCBMIC
| | | | | | | +----- 1
| | | | | | +-------- 0
| | | | | +----------- 0
| | | | +-------------- 0
| | | +----------------- 0
| | +-------------------- 0
| +----------------------- 0
+-------------------------- 1
Bits 0-7, Gate Array Identifications
For the RCBMIC gate array, the value read will be 81h.
RCBMIC
Power-up: 1000 0001
Reset command: SSSS SSSS
The INITREG0, 1, and 3 registers are co-processor adapter and system unit read/write registers. INITREG2 is a system unit read-only register. These registers initialize the gate array for proper operation. Bits from POS2, 4, and 5 are mapped into INITREG0 and 3, and bit 2 of INITREG1. INITREG1 should be programmed by the co-processor adapter.
I/O Addresses
-------------
Co-Processor Adapter
INITREG0 = 0004h
INITREG1 = 0006h
INITREG3 = 001Ah
System Unit
(INITREG0) PTRREG = 0012h
(INITREG1) PTRREG = 0010h
(INITREG2) PTRREG = 0008h
(INITREG3) PTRREG = 0013h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ INITREG0 INITREG1 INITREG2 INITREG3
| | | | | | | |
| | | | | | | +----- L1 CS L1 W1
| | | | | | +-------- L2 AW L2 W2
| | | | | +----------- L4 RSVD L4 W4
| | | | +-------------- SE M1 0 FE
| | | +----------------- C1 DE 0 B0
| | +-------------------- C2 M2 0 B1
| +----------------------- C4 RR 0 B2
+-------------------------- RSVD DR 0 B3
POS2 is mapped into INITREG0. When either the INITREG0 address or
the POS address is used, the same register is accessed.
POS4 bits 5, 6, and 7 are mapped to INITREG3 bits 0, 1, and 2.
POS5 bits 0, 1, 2, 3, and 4 are mapped to INITREG3 bits 3, 4, 5, 6, and
7. POS5 bit 5 is mapped to INITREG1 bit 2;
this bit is read-only from the 80C186 side.
Bits 0-2, Interrupt Level
These bits determine the interrupt level that the co-processor adapter
will operate on within the system unit environment.
+----------+-----------------+
| | Interrupt Level |
| L4 L2 L1 | (Decimal) |
+----------+-----------------+
| 0 0 0 | 3 |
| 0 0 1 | 4 |
| 0 1 0 | 7 |
| 0 1 1 | 9 |
| 1 0 0 | 10 |
| 1 0 1 | 11 |
| 1 1 0 | 12 |
| 1 1 1 | Reserved |
+----------+-----------------+
Bit 3, Sleep Enable
Bits 4-6, Card Number
These bits specify the system unit base I/O address for all
system unit RAM controller and bus master interface chip I/O registers. Each card should
have a unique address, compared with each other
and any other attachment in the system unit
These bits are not available in INITREG2.
+-------------+----------+
| | Base |
| C8 C4 C2 C1 | Address |
+-------------+----------+
| 0 0 0 0 | 02A0h |
| 0 0 0 1 | 06A0h |
| 0 0 1 0 | 0AA0h |
| 0 0 1 1 | 0EA0h |
| 0 1 0 0 | 12A0h |
| 0 1 0 1 | 16A0h |
| 0 1 1 0 | 1AA0h |
| 0 1 1 1 | 1EA0h |
+-------------+----------+
Bit 7, Reserved (RSVD)
Bit 0, Card-Selected Feedback-Return Indicator
Setting this bit to 1
masks the NMI condition that is possible when the
bus master does not receive a card-selected feedback-return signal
during a bus cycle on the Micro Channel.
Clearing this bit, allows an NMI to the 80C186.
In either case, the CSFDBKRTN bit in the NMISTAT is set.
This bit also is addressable as bit 10 in the NMIMASK register.
Bit 1, Add Wait State
When set to 1, this bit adds one wait state to each bus master cycle.
This bit is used in some systems to provide additional time for devices
in the system to return IOCHRDY.
Bit 2, Reserved (RSVD)
This bit should be programmed to 0.
Bits 3 & 5, Memory Size
See the following figure.
Figure 36. INITREG1 (Bits 3 & 5) Memory Size
+-------+-------+---------------+
| Bit 5 | Bit 3 | Memory Size |
+-------+-------+---------------+
| 0 | 0 | 1 megabyte |
| 0 | 1 | Reserved |
| 1 | 0 | 512 kilobytes |
| 1 | 1 | 2 megabytes |
+-------+-------+---------------+
Bit 4, DMAPG Enable
Bit 6, PROM Ready
This bit is reset by a power-up or reset command.
It is the responsibility of PROM to set this bit to 1 after
it is ready. This bit may be cleared by PROM, if desired.
Bit 7, Double Refresh Time
When this bit is set to 1, the refresh rate is 13.4 microseconds.
When the bit is reset to 0, the refresh rate is 6.7 microseconds.
Bits 0-2, Window Size
The logical state of these bits selects the window size
that the system unit views at any one time.
A window size of 8 kilobytes is the default for compatibility.
+----------+---------------+
| W4 W2 W1 | Window Size |
+----------+---------------+
| 0 0 0 | 8 kilobytes |
| 0 0 1 | 16 kilobytes |
| 0 1 0 | 32 kilobytes |
| 0 1 1 | 64 kilobytes |
| 1 0 0 | 128 kilobytes |
| 1 0 1 | 512 kilobytes |
| 1 1 0 | 1 megabyte |
| 1 1 1 | 2 megabytes |
+----------+---------------+
Bit 3, Fairness Enable
Bits 4-7, Arbitration Level
These bits determine the system unit bus arbitration level
for the co-processor adapter card.
They are binary encoded with B7 as the MSB and B4 as the LSB.
INITREG0 INITREG1 INITREG2 INITREG3
Power-up: 0000 0000 0000 0000 0000 0000 0000 0000
Reset command: SSSS SSSS SSSS SSSS SSSS SSSS SSSS SSSS
The INTIDREG register is a co-processor adapter read/write status register. It supplies the co-processor adapter with 16 independent interrupt status bits, each of which is separately addressable from the system unit. This allows separate system unit bus masters or tasks to own one or more status bits to interrupt the 80C186. PTRREG values 40h-4Fh are assigned to bits 0-15, respectively. A write of one of these values to the PTRREG sets the respective bit in the INTIDREG. The INTCOM (PTRREG = 09H) is also assigned to bit 15 for compatibility with previous products. A logical OR of these bits is used to cause an interrupt to the 80C186. This register must be read by the interrupt routine to determine the interrupting source (there may be more than one).
Clearing of the interrupting sources is done by writing the register with the complement of the value that was read. All bits must be complemented; if not, an interrupt is regenerated after the EOI. For example, reading a binary value of 0111000001000001 means that five different system unit sources have interrupts pending for the co-processor adapter card. A binary value of 1000111110111110 is written back to allow further interrupts by those sources. This write should be followed by the 80C186 EOI command.
I/O Addresses
-------------
Co-Processor Adapter
INTIDREG = 0092h, 16-bit R/W
System Unit = None
+---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--+
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
+-+-+-+-+-+-+-+-+-+-+-+-++-++-++-++-++-++-++-++-++-++-+
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +--- ID0
| | | | | | | | | | | | | | +------ ID1
| | | | | | | | | | | | | +--------- ID2
| | | | | | | | | | | | +------------ ID3
| | | | | | | | | | | +--------------- ID4
| | | | | | | | | | +------------------ ID5
| | | | | | | | | +--------------------- ID6
| | | | | | | | +------------------------ ID7
| | | | | | | +--------------------------- ID8
| | | | | | +------------------------------ ID9
| | | | | +--------------------------------- ID10
| | | | +------------------------------------- ID11
| | | +----------------------------------------- ID12
| | +--------------------------------------------- ID13
| +------------------------------------------------- ID14
+----------------------------------------------------- ID15
Bits 0-15
Each bit is a status bit that is set when 1 of
16 I/O write commands is performed by a system unit bus master.
The data value contained in the I/O write command
determines which bit is set.
Power-up: 0000 0000 0000 0000
Reset command: 0000 0000 0000 0000
This register is read after an 80C186 INT0 interrupt. It works in combination with INTIDREG. Both bus master terminal count interrupts and system-unit-initiated interrupts are presented to the 80C186 through these two registers. Three different values can be read from this register after an interrupt, 01h, 02h, or 03h. If 01h is read, a system-unit-initiated interrupt is pending for the card. INTIDREG must now be read to determine which of 16 possible sources of interrupts are pending. Clearing INTIDREG (see "Interrupt Identifier Register (INTIDREG)"
If 02h is read from INT0STAT, a bus master terminal count interrupt is pending for the 80C186. After this interrupt is serviced, bit 1 is cleared by writing FDh (complement of 02h) back to INT0STAT.
If 03h is read from INT0STAT, both a bus master terminal count and system-unit-initiated interrupts are pending for the 80C186. If the software chooses to service both interrupts before the 80C186 EOI command is issued, it must clear both INTIDREG and INT0STAT, as described above.
The only value that should ever have to be written back to the INT0STAT is FDh. All other interrupts are cleared through INTIDREG.
I/O Addresses
-------------
Co-Processor Adapter
INTOSTAT = 90h
System Unit = None
+---+---+---+---+---+---+---+---+
|IT7|IT6|IT5|IT4|IT3|IT2|IT1|IT0|
+---+---+---+---+---+---+---+---+
Bit 0, INTCOM Identifier
If this bit is set to 1, some bus
master, host, or other source is interrupting the co-processor adapter. The
interrupt routine should read INTIDREG to identify the interrupting bus
master.
Bit 1, BM CH Interrupt
If this bit is set to 1, the bus master channel has reached the
terminal count.
Bits 2-7, Reserved
These bits are reserved.
Power-up: 0000 0000
Reset command: 0000 0000
This single-bit read/write register is used to cause an I/O channel check to the system processor under program control.
I/O Addresses
-------------
Co-Processor Adapter
IOCHCK = 0094h
System Unit = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ IOCHCK
| | | | | | | |
| | | | | | | +----- K0
| | | | | | +-------- K1
| | | | | +----------- K2
| | | | +-------------- K3
| | | +----------------- K4
| | +-------------------- K5
| +----------------------- K6
+-------------------------- K7
Bit 0, I/O Channel Check
When set to 1, this bit causes an I/O channel check to the host system.
When reset to 0, it terminates the I/O channel check to the system.
This bit is reset either directly under 80C186 control, or by the host
setting bit 7 of POS 5 to a 1, which terminates the channel check.
Bits 1-7, Reserved
These bits are reserved.
Power-up: 0000 0000
Reset command: 0000 0000
The location registers are system unit and co-processor adapter read/write registers. They provide the user with the option to place the co-processor adapter's memory anywhere within each of the following four 16MB blocks on a boundary defined by W4, W2, and W1 in INITREG3:
I/O Addresses
-------------
Co-Processor Adapter
LOCREG0 = 0000h
LOCREG1 = 0002H
System Unit
LOCREG0 = Base + 0000h
LOCREG1 = Base + 0001h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0| POS3 POS4
+-++-++-++-++-++-++-++-++ LOCREG0 LOCREG1
| | | | | | | |
| | | | | | | +----- A13 A21
| | | | | | +-------- A14 A22
| | | | | +----------- A15 A23
| | | | +-------------- A16 A30
| | | +----------------- A17 A31
| | +-------------------- A18 0
| +----------------------- A19 0
+-------------------------- A20 0
Bits 0-7, Address
LOCREG0 must match the system unit address bits A20 to A13
to access the co-processor adapter RAM. This value is where the user
desires the co-processor adapter to be located within the system unit memory map.
If the window size is changed dynamically, the user must keep track of the new window boundary. For example, if there is an 8KB window initially at C200h segment (61h), and the window size is changed to 16KB, the new segment is located at C000h (60h). Therefore, the lower boundary has changed.Reset Conditions
Power-up: UUUU UUUU
Reset command: SSSS SSSS
Bits 0-7, Address
LOCREG1 is a continuation of LOCREG0.
The user should program the value that corresponds to the desired
location for the co-processor adapter within the system unit memory map.
Reset Conditions
Power-up: 000U UUUU
Reset command: SSSS SSSS
The NMIMASK is a co-processor adapter read/write register. Its purpose is to allow masking of various internal interrupts from causing an NMI to the co-processor adapter's microprocessor. Bits 6 are 7 are command features for the co-processor adapter, and bit 8 is an enable/disable bit for the diagnostic address compare (DAC) feature.
I/O Addresses
-------------
Co-Processor Adapter
NMIMASK = 0008h, 16-bit R/W
System Unit = None
+---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--+
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
+-+-+-+-+-+-+-+-+-+-+-+-++-++-++-++-++-++-++-++-++-++-+
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +--- CRST
| | | | | | | | | | | | | | +------ WD
| | | | | | | | | | | | | +--------- PE
| | | | | | | | | | | | +------------ PCC
| | | | | | | | | | | +--------------- NC
| | | | | | | | | | +------------------ WP/RWP
| | | | | | | | | +--------------------- DG
| | | | | | | | +------------------------ FP
| | | | | | | +--------------------------- DAC
| | | | | | +------------------------------ EXT PCC
| | | | | +--------------------------------- CSFDBKRTN
| | | | +------------------------------------- PAREN
| | | +----------------------------------------- ARB LVL
| | +--------------------------------------------- LC
| +------------------------------------------------- RSVD
+----------------------------------------------------- RSVD
Bit 0, Channel Reset Mask
When a system unit channel reset occurs during a warm start,
the co-processor adapter has the option of masking this status
from creating an external NMI by setting this bit to 1.
If this bit is reset to 0, an NMI is created when
this condition occurs. In all cases, a channel reset NMI is
posted in the NMISTAT register.
Bit 1, Watchdog Timer Mask
The RAM controller and bus master interface chip monitors the watchdog timer on the co-processor adapter.
When the watchdog timer has an error, the co-processor adapter
has the option of masking this status from creating
an NMI by setting this bit to 1. If this bit is reset to 0
and a watchdog error occurs: (1) an NMI is
created, (2) the task register is loaded with FEh,
and (3) a system unit interrupt is generated.
If the watchdog timer error mask bit is set to 1: (1) the NMI is
blocked, (2) the task register is not loaded, and (3) a
system unit interrupt is not generated.
In either case, a WD bit is posted in the NMISTAT register.
Bit 2, Co-Processor Adapter Parity Error Mask
When the co-processor adapter microprocessor or the DMA cycle has a parity error,
the co-processor adapter has the option of masking
this status from creating an NMI by setting this bit to 1.
If this bit is reset to 0, an NMI is created when a parity error occurs.
In either case, a PE bit is posted in the NMISTAT register.
Bit 3, System Unit I/O Channel Check Mask
The RAM controller and bus master interface chip monitors the system unit I/O channel check line.
The co-processor adapter has the option of masking this status
from creating an NMI by setting this bit to 1.
If this bit is reset to 0, an NMI is
created when this line is active. In either case,
the PCC bit is posted in the NMISTAT register.
Bit 4, NMI Command Mask
An NMI command may be given by the system unit through its COMREG register.
The co-processor adapter has the option of masking this command from creating an NMI by
setting this bit to 1. If this bit is reset to 0, an NMI
is created when the system unit issues this command.
In either case, the NMI command is posted in the NMISTAT register.
Bit 5, Translate Table Write Protect, Read/Write Protect
Mask
Setting this bit to 1 blocks a translate table read or read/write
violation from causing an NMI. These violations occur when a read or
read/write protect bit is set in an entry of the translate table, and
a read or read/write access is attempted to a protected block of
memory.
If this bit is reset to a 0, either violation causes an NMI. In either case, the WP bit is posted in the NMISTAT register.
Bit 6, Degate RAM
Setting this bit to 1 deactivates the RAM (does not allow
access of the RAM) from the system unit microprocessor. This bit is dual
purpose in that it is set to 1 if the system unit has its
identical degate RAM bit (in the COMREG) active.
This bit only reads a 0 when both the co-processor adapter and the system unit have
written 0s into their respective bits, as indicated in
Figure 37.. Caution should be exercised when using this bit.
Undetermined behavior of the RAM controller and bus master interface chip occurs if this bit is set during a
system unit memory read or memory write cycle.
Figure 37. NMIMASK Bit 6 Description
System Unit System Unit
Write -----------+ Read -------------+
| | System Unit
System Unit +--+--+ +--+---+ Data Bit
Data Bit | | +----+ | | (DG)
(DG) ---->|Latch+--->| | +--->|Buffer+--------->
| | | | | | |
+-----+ | | DG Internal | +------+
| | Control Bit |
| OR +-------------+ Co-Processor
Co-Processor | | | Adapter
Adapter +-----+ | | | +------+ Data Bit
Data Bit | | | | | | | (DG)
(DG) ---->|Latch+--->| | +--->|Buffer+--------->
| | +----+ | |
Co-Processor +--+--+ Co-Processor +--+---+
Adapter | Adapter |
Write -----------+ Read -------------+
IF . . . THEN . . .
+-----------------------------+ +----------------------------+
| System Unit AND Co-Proc | | System Unit AND Co-Proc|
| Writes Writes | | Reads Reads |
+-----------------------------+ +----------------------------+
| 0 & 0 | | 0 & 0 |
| 0 & 1 | | 1 & 1 |
| 1 & 0 | | 1 & 1 |
| 1 & 1 | | 1 & 1 |
+-----------------------------+ +----------------------------+
Bit 7, Force Bad Parity
Figure 38. NMIMASK Bit 7 Description
System Unit System Unit
Write -----------+ Read -------------+
| | System Unit
System Unit +--+--+ +--+---+ Data Bit
Data Bit | | +----+ | | (FP)
(FP) ---->|Latch+--->| | +--->|Buffer+--------->
| | | | | | |
+-----+ | | FP Internal | +------+
| | Control Bit |
| OR +-------------+ Co-Proc
Co-Processor | | | Adapter
Adapter +-----+ | | | +------+ Data Bit
Data Bit | | | | | | | (FP)
(FP) ---->|Latch+--->| | +--->|Buffer+--------->
| | +----+ | |
Co-Processor +--+--+ Co-Processor +--+---+
Adapter | Adapter |
Write -----------+ Read -------------+
IF . . . THEN . . .
+-----------------------------+ +----------------------------+
| System Unit AND Co-Proc | | System Unit AND Co-Proc|
| Writes Writes | | Reads Reads |
+-----------------------------+ +----------------------------+
| 0 & 0 | | 0 & 0 |
| 0 & 1 | | 1 & 1 |
| 1 & 0 | | 1 & 1 |
| 1 & 1 | | 1 & 1 |
+-----------------------------+ +----------------------------+
Bit 8, Diagnostic Address Compare
Bit 9, External Channel Check Indicator
Setting this bit to 1
masks the NMIs to the 80C186 which result from
I/O channel checks that occur while the co-processor adapter is performing bus master
transfers on the Micro Channel. Clearing this bit, allows NMIs to the
80C186, if the I/O channel check is asserted during co-processor adapter bus master
operation. In either case, the EXT PCC bit in the NMISTAT is set to 1.
Bit 10, Card-Selected Feedback-Return Indicator
Setting this bit to 1
masks the NMI condition that is possible when the
bus master does not receive a card-selected feedback-return signal
during a bus cycle on the Micro Channel.
Clearing this bit, allows an NMI to the 80C186.
In either case, the CSFDBKRTN bit in the NMISTAT is set to 1.
Bit 11, Parity Latch Enable
When set to 1, this bit enables the
PCPARs, the RICPARs and the PESTAT registers to capture
information associated with a parity error, such as address and source.
When reset to 0, the PCPARs, the RICPARS, and the PESTAT registers
are not updated when a parity error occurs.
This mode allows the DAC function to be used solely as
a memory protection feature.
Bit 12, Loss of Arbitration Level
Setting this bit to 1 disables the detection of a change in Micro
Channel
arbitration level in POS, and masks the NMI condition that occurs
when a change is detected.
Resetting this bit to 0, enables the detection of a change, and allows
this condition to force an NMI to the 80C186.
The bus master channel is stopped if a change of arbitration level
is detected.
Bit 13, Loss of Channel
Setting this bit to 1 masks the NMIs to the 80C186 that are
caused by a loss of the Micro Channel.
The Micro Channel is lost by either the raising of the ARB/GNT signal
on the Micro Channel during bus master operation, or the loss of the
sleep/enable in POS.
Either of these conditions stops any bus master activity.
Bits 14-15, Reserved
These bits are reserved.
Power-up: 0000 1111 0011 1111
Reset command: 0000 1111 0011 1111
The NMISTAT is a co-processor adapter read-only register. Its purpose is to provide status of the various NMIs that can occur, regardless of whether or not the various NMIs are masked from the 80C186. All status bits are set in this way, except for the DAC status bit (bit 8), which is not set if the DAC condition is masked in the NMIMASK. Once a bit is active, the co-processor adapter must read the NMISTAT, and the status must go inactive. Then, the status may go active to be detected once again. Two bits are not NMI status bits but system unit interrupt status bits. Bits 2 and 3 of this register work in conjunction with the PESTAT and PCCSTAT registers, respectively. These registers contain secondary status, which further defines the PE and PCC bits.
I/O Addresses
-------------
Co-Processor Adapter
NMIMASK = 000Ah, 16-bit read-only
System Unit = None
+---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--+
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
+-+-+-+-+-+-+-+-+-+-+-+-++-++-++-++-++-++-++-++-++-++-+
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +--- CRST
| | | | | | | | | | | | | | +------ WD
| | | | | | | | | | | | | +--------- PE
| | | | | | | | | | | | +------------ PCC
| | | | | | | | | | | +--------------- NC
| | | | | | | | | | +------------------ WP/RWP
| | | | | | | | | +--------------------- DG
| | | | | | | | +------------------------ IE
| | | | | | | +--------------------------- IS
| | | | | | +------------------------------ EXT PCC
| | | | | +--------------------------------- CSFDBKRTN
| | | | +------------------------------------- ARB LVL
| | | +----------------------------------------- LC
| | +--------------------------------------------- RSVD
| +------------------------------------------------- RSVD
+----------------------------------------------------- RSVD
Bit 0, Channel Reset Status
If this bit is set to 1, the system unit had
a channel reset from a warm start.
This bit is cleared by reading this
register, which also terminates the NMI.
Bit 1, Watchdog Timer Error Status
If this bit is set to 1, the co-processor adapter had a watchdog timer error.
This bit is cleared by
reading this register, which also terminates the NMI.
Bit 2, Co-Processor Adapter Parity Error Status
If this bit is set to 1, the co-processor adapter had a parity error.
This bit is cleared by reading this
register, which also terminates the NMI.
Bit 3, System Unit I/O Channel Check Status
If this bit is set to 1, the system unit had a parity error
during DRAM access. This bit is cleared by reading this register,
which also terminates the NMI.
Bit 4, NMI Command Status
If this bit is set to 1, the system unit has issued an NMI command.
This bit is cleared by reading this
register, which also terminates the NMI.
Bit 5, Translate Table Write Protect, Read/Write Protect
Status
If this bit is set to 1, either a write protect or a read/write protect
error has occurred in bankswitched memory.
This bit is cleared by reading this
register, which also terminates the NMI.
Bit 6, Interrupt Enable
If this bit is set to 1, system unit interrupts are enabled.
Bit 7, Interrupt Pending
If an interrupt is pending for the system unit, IP=1.
It is cleared by reading the task register.
Bit 8, Diagnostic Address Compare
If this bit is set to 1, an address compare has occurred for the
prespecified source of comparison.
The bit is cleared by reading the NMISTAT register.
Bit 9, External I/O Channel Check Indicator
If this bit is set to 1, an I/O channel check has occurred on
the Micro Channel while the co-processor adapter card is a bus master.
The bit is cleared by reading the NMISTAT register.
Bit 10, Card-Selected Feedback-Return Indicator
If this bit is set to 1,
the card-selected feedback-return signal on the
Micro Channel was not detected during a bus master cycle.
The bit is cleared by reading the NMISTAT register.
Bits 11-15, Reserved
These bits are reserved.
Power-up: 0000 0000 0000 0000
Reset command: 0000 0000 0000 0000
The PCCSTAT register is a secondary NMI status register that is read when the PCC bit in the NMISTAT register is read as a 1. The contents of this register are updated only when some parity condition causes the NMISTAT PCC bit to be set to 1. The PCCSTAT register identifies which source was accessing the RAM when the parity error occurred.
I/O Addresses
-------------
Co-Processor Adapter
PCCSTAT = 008Ah
System Unit
PCCSTAT = Use DREG with PTRREG preset to 0014h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ PCCSTAT
| | | | | | | |
| | | | | | | +----- C0
| | | | | | +-------- C1
| | | | | +----------- C2
| | | | +-------------- C3
| | | +----------------- C4
| | +-------------------- C5
| +----------------------- C6
+-------------------------- C7
Bits 0-2, Reserved
These bits are reserved.
Bits 3-6, ARB Level Identifier
These bits represent the binary encoded ARB level that was present on
the Micro Channel at the time of the parity error.
Bit 6 is the most significant bit.
Bit 7, Write IO/CHCHK Indicator
This bit is set to 1 when an IO/CHCHK occurs
as a result of writing to the IOCHCK register.
Power-up: 0UUU UUUU
Reset command: 0SSS SSSS
These registers are dual-function read/write registers.
For the first function, PCPAR0, 1, and 2 are used to capture the system unit address and status at which a parity error occurs. The data in these registers is only valid after an error. To clear the internal circuitry and allow for further parity checking, a system unit memory write to any location of the co-processor adapter must be performed, or POS5 bit 7 must be written with a 1. These registers should be used in conjunction with the CPUPG register to determine exactly where the error occurred, and also in conjunction with the PCCSTAT register to determine the source of the parity error.
The second function of these registers is to work in conjunction with the RICPAR registers to provide an address-range mask and source-compare mask capability. In this mode, PCPAR0 and PCPAR1 are written with 1s (in ascending order from Bit 0) to mask off address ranges in powers of 2. In this way, the compare can occur on one byte, or in a range from 2 to 64KB. The six bits of PCPAR2 are used as the source-compare mask and the function-select bits for the DAC feature.
Bit 0 = 0 = Monitor all accesses Bit 0 = 1 = Monitor only write accesses Bit 1 = 1 = Monitor 80C186 accesses Bit 2 = 1 = Monitor memory slave accesses Bit 3 = 1 = Monitor backend DMA accesses Bit 4 = 1 = Monitor CH1/CH2 accesses Bit 5 = 0 = Do not block the memory write attempt Bit 5 = 1 = Block the memory write attempt.
I/O Addresses
-------------
Co-Processor Adapter
PCPAR0 = 0096h
PCPAR1 = 0098h
PCPAR2 = 009Ah
System Unit = None
PCPAR0 = Use DREG With PTRREG Preset to 000Ah
PCPAR1 = Use DREG With PTRREG Preset to 000Bh
PCPAR2 = Use DREG With PTRREG Preset to 0011h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ PCPAR0 PCPAR1 PCPAR2*
| | | | | | | |
| | | | | | | +----- A0 A8 A16
| | | | | | +-------- A1 A9 A17
| | | | | +----------- A2 A10 A18
| | | | +-------------- A3 A11 A19
| | | +----------------- A4 A12 A20
| | +-------------------- A5 A13 IEN
| +----------------------- A6 A14 MODE
+-------------------------- A7 A15 CKI
* The format shown for PCPAR2 is for system unit accesses only.
Bits 0-7, System Unit Address Bits
These bits represent the address at which a parity error occurred.
Bits 0-4, System Unit Address
These bits represent the rest of the address
at which a parity error occurred.
Bits 5-7, System Unit Address Bits
These bits are available only when an expanded
window size is being used.
Bits 0-4, System Unit Address Bits
These bits are available only when an expanded
window size is being used.
Bit 6, Mode
When set to 1, a pulse is generated on the I/O channel check line.
When reset to 0, the I/O channel check is held low until released
by program control. The default is reset.
Bit 7, I/O Channel Check Indicator (CKI)
This bit is read-only; it indicates if an
I/O channel check condition exists
as a result of a slave RAM error.
This bit always indicates status, regardless of the state
of bit 5. To clear this bit, write to
any memory location in the co-processor adapter memory.
Also, either a channel reset or writing a 1 to POS5, bit 7
clears this bit. CKI is the inversion of POS5 bit 7, NCKI.
PCPAR0, 1 PCPAR2
Power-up: UUUU UUUU 011U UUUU
Reset command: SSSS SSSS SSSS SSSS
A Micro Channel slave detecting a Micro Channel parity error latches the physical RAM address, not the Micro Channel address.
The PESTAT register is a secondary NMI status register that is read when the PE bit or the DAC bit in the NMISTAT register is read as a 1. The contents of this register are valid when some parity condition causes the NMISTAT PE bit to be set to 1. This register identifies which source was accessing RAM when the parity error occurred. This register also is valid after the DAC bit of the NMISTAT register is set. The PESTAT register is re-enabled to capture further information after the RICPAR2 register is read by software.
I/O Addresses
-------------
Co-Processor Adapter
PESTAT = 008Ch, 16-bit read-only
System Unit = None
+---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--+
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
+-+-+-+-+-+-+-+-+-+-+-+-++-++-++-++-++-++-++-++-++-++-+ PESTAT
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | +--- P0
| | | | | | | | | | | | | | +------ P1
| | | | | | | | | | | | | +--------- P2
| | | | | | | | | | | | +------------ P3
| | | | | | | | | | | +--------------- P4
| | | | | | | | | | +------------------ P5
| | | | | | | | | +--------------------- P6
| | | | | | | | +------------------------ P7
| | | | | | | +--------------------------- P8
| | | | | | +------------------------------ P9
| | | | | +--------------------------------- P10
| | | | +------------------------------------- P11
| | | +----------------------------------------- P12
| | +--------------------------------------------- RSVD
| +------------------------------------------------- RSVD
+----------------------------------------------------- RSVD
Bits 0-1, Local Master Encoded
These bits represent the binary encoded value of the local master at the
time of the parity error:
Bits 4-7, DMA/Peripheral Interface Chip DMA Channel Number Encoded
These bits represent the binary encoded DMA channel number that was
controlling the local bus at the time of the parity error or DAC.
Bit 7 is the most significant bit.
Bit 8
This bit is valid only after a DAC has occurred. If this bit is set to
1, the DAC source is either the host processor or some other system
bus master. If this bit is reset to 0,
bits 0-1 contain the encoded source of the DAC.
Bits 9-12
These bits are only valid after a DAC has occurred.
If bit 8 is set to 1,
these bits contain the ARB level of the master on the
bus when the DAC occurred.
If bit 8 is reset to 0, these bits are not valid.
Bits 13-15, Reserved
These bits are reserved.
Power-up: 000U UUUU UUUU UUUU
Reset command: 000S SSSS SSSS SSSS
The PROCSYNC register is a co-processor adapter and a system unit read/write register. This register allows the co-processor adapter and the system unit processors to synchronize their activities by the use of a simple read-modify-write mechanism. The mechanism is defined as follows:
I/O read of 00h data defines *------> Ownership I/O read of FFh data defines *------> No Ownership I/O write (any data) *------> Releases OwnershipThe hardware guarantees that both processors cannot read 00 simultaneously. The definition of what is "owned" is left up to the user's application.
I/O Addresses
-------------
Co-Processor Adapter
PROCSYNC = 008Eh
System Unit = Base + 0007h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ PROCSYNC
| | | | | | | |
| | | | | | | +----- D0
| | | | | | +-------- D1
| | | | | +----------- D2
| | | | +-------------- D3
| | | +----------------- D4
| | +-------------------- D5
| +----------------------- D6
+-------------------------- D7
Bits 0-7, Data Bits
These bits determine "ownership".
Reading a 00h defines "ownership".
Reading an FFh defines "no ownership".
An I/O write (any data) "releases ownership".
Power-up: 0000 0000
Reset command: 0000 0000
The RICPAR registers are dual-function co-processor adapter read/write registers.
The first function of these registers is to capture the address of a co-processor adapter parity error or translate table protection violation. This mode (mode 1) is enabled by setting bit 11 of the NMIMASK register to 1. If the parity error occurs during an 80C186 memory read cycle, the logical address (pretranslated) is captured. If the parity error occurs during a DMA/peripheral interface chip DMA read cycle or a BMCH1 read cycle, the physical memory address is captured. If a translate table protection violation occurs, the logical address (pretranslated) is captured. The data in these registers has the above meaning only if the PE bit in the NMISTAT register is set. The source of the latched address is encoded in information in the PESTAT register. In order for internal circuitry to be cleared and to allow for further parity checking, PAR2 must be read. It is suggested that PAR0 and PAR1 be read before PAR2, since the PAR2 read unlocks all three registers to capture an address if another error should occur. Also, the PESTAT register should be read before PAR2 because the information latched in this register can again be updated once PAR2 has been read.
The second function of these registers is to provide a 21-bit diagnostic address compare function. This mode (mode 2) is enabled by resetting bit 8 of the NMIMASK register. In this mode, these registers are programmed with a physical memory address value which specifies the base address for a compare. The range of addresses on which a compare will occur is programmed in PCPAR 0 and 1. This range can be a single byte or up to a range of 64KB. Also, the different possible address sources of a compare can be masked on or off in PCPAR 2. Once a compare has occurred, the RICPAR register are written over with the actual compare address. Also, after a compare, the PESTAT is updated with DAC-specific information.
Both the parity capture mode and the DAC capture mode can be enabled at the same time (mode 3). In this mode, the RICPAR and PCPAR registers are programmed as specified above for the DAC mode. If a system unit parity error occurs prior to the DAC, the parity address is latched in the PCPAR registers, thereby corrupting the range checking and source mask data. The hardware automatically disables the DAC function at this point until the parity error is cleared by software to prevent erroneous DACs from occurring. Likewise, if an 80C186-associated error (as described above) occurs prior to the DAC, the parity address is latched in the RICPAR registers, thereby corrupting the base DAC address. The hardware automatically disables the DAC function at this point until the parity error is cleared by reading RICPAR 2. This again prevents erroneous DACs from occurring.
I/O Addresses
-------------
Co-Processor Adapter
RICPAR0 = 000Ch
RICPAR1 = 000Eh
RICPAR2 = 0010h
System Unit = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ RICPAR0 RICPAR1 RICPAR2
| | | | | | | |
| | | | | | | +----- A0 A8 A16
| | | | | | +-------- A1 A9 A17
| | | | | +----------- A2 A10 A18
| | | | +-------------- A3 A11 A19
| | | +----------------- A4 A12 A20
| | +-------------------- A5 A13 0
| +----------------------- A6 A14 0
+-------------------------- A7 A15 0
Bits 0-7, Co-Processor AdapterAddress Bits
In mode 1, these bits represent the address at which a
parity error or translate table protection violation has occurred.
In mode 2, these bits are programmed with the base address of a DAC
address range.
Reset Conditions
RICPAR0 RICPAR1
Power-up: UUUU UUUU UUUU UUUU
Reset command: SSSS SSSS SSSS SSSS
Bits 0-4, Co-Processor Adapter Address Bits
In mode 1, these bits represent the remainder of the address at which a
parity error or translate table protection violation has occurred.
In mode 2, these bits are programmed with the remainder of the
base address of a DAC address range.
Bits 5-7, Reserved
These bits are reserved.
Reset Conditions
RICPAR2
Power-up: 000U UUUU
Reset command: 000S SSSS
The TREG register is a system unit and co-processor adapter read/write register. This register functions as a mailbox, passing data primarily from the co-processor adapter to the system unit. Writing to this register from either the system unit or the co-processor adapter generates an interrupt for the system unit (maskable by the IE bit). To clear the interrupt, either the system unit or the co-processor adapter must read the TREG register.
In addition, the act of reading this register changes the value of the register to FFh. A watchdog timer error also changes the value of the register to FEh, but any data written to the task register before or after the watchdog timer error occurred is saved.
After the FEh is read, the data may be read from the TREG register. All interrupt functions explained above hold true for the watchdog timer error (as if the TREG register was written to). The user should be aware that if a simultaneous write by the system unit and the co-processor adapter occurs, the value of the register is uncertain. TREG is available on the 80C186 side at 0016h (read-only) for manufacturing tests only. This is a direct tap of the register, and reading it does not change the value of the TREG register, as does a read of the real TREG address. A Micro Channel reset changes the value back to FFh.
I/O Addresses
-------------
Co-Processor Adapter
TREG = 0012h, 0016h
System Unit
TREG = Base + 0004h
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ TREG
| | | | | | | |
| | | | | | | +----- T0
| | | | | | +-------- T1
| | | | | +----------- T2
| | | | +-------------- T3
| | | +----------------- T4
| | +-------------------- T5
| +----------------------- T6
+-------------------------- T7
Bits 0-7, Task Register Data
Any value that the user wishes to pass except:
To
+--------+ +---------+ Co-Processor
| | | | Adapter
FFh --->| | TREG | Content |------------->
| Multi- | Value | of TREG | To System
(Latched T0-T7 --->| plexer |------->| at Time | Unit
Data) | | | of Read |------------->
FEh --->| | | |
+-+----+-+ +---------+
| |
Watchdog | |
Error -------+ |
|
Data Present ------------+
+-----------+---------------+-----------------+
| Watchdog | Data | TREG Value |
| Error | Present | At Time of Read |
+-----------+---------------+-----------------+
| No | No ----------> FFh |
| No | Yes ----------> T0-T7 |
| Yes | No ----------> FEh |
| Yes | Yes ----------> FEh |
+-----------+---------------------------------+
Power-up: 1111 1111
Reset command: 1111 1111
See "Memory Address Translation" for details.
The TTPROTON register is a co-processor adapter write-only register. When an I/O write command is issued to this register, the read/write and write protect bits written into the translate table entries provide the protection specified by the setting of those bits. This register works in conjunction with the translate table protection off register described in "Translate Table Protection Off Register (TTPROTOFF)". The data associated with the I/O write command is don't care.
I/O Addresses
-------------
Co-Processor Adapter
TTPROTON = 009Ch
System Unit = None
Power-up: Protection associated with
Translate Table enabled.
Reset command: Protection associated with
Translate Table enabled.
The TTPROTOFF register is a co-processor adapter write-only register. When an I/O write command is issued to this register, the read/write and write protect bits written into the translate table entries are blocked from providing the protection specified by the setting of those bits. This register works in conjunction with the translate table protection on register described in "Translate Table Protection On Register (TTPROTON)". The data associated with the I/O write command is don't care.
I/O Addresses
-------------
Co-Processor Adapter
TTPROTOFF = 009Eh
System Unit = None
Power-up: Protection associated with
Translate Table enabled.
Reset command: Protection associated with
Translate Table enabled.
This section describes in detail the registers contained within the DMA/peripheral interface chip.
All registers are byte read and write, unless otherwise noted. All unused addresses should be considered as reserved. Bits are described with bit 0 as the least significant bit.
Both power-up reset and command reset values are shown in the "reset condition" section of each register. In these sections, bits shown with "U" represent an undefined or unpredictable state after power-up or reset commands. Bits that are designated with "S" remain in the same state as before the reset command.
This register is used to assign different operating modes to the DMA/peripheral interface chip. It is an 8-bit read/write register at I/O address 8212h.
I/O Addresses
-------------
Co-Processor Adapter
DMAASSIGN = 8212h
System Unit = None
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| CH3| CH2| CH1| CH0|RSVD| AS2| AS1| AS0|
+----+----+----+----+----+----+----+----+
Bit 0, AS0
When this bit is set to 1,
it assigns two DMA channels per transmit and receive port for the
first four ports. When this bit is reset to 0,
it assigns one DMA channel per transmit and receive port for eight ports.
Bit 1, Receive/Transmit Interrupt Priority Select
This bit selects whether all receive channels interrupt on a higher
priority than transmit channels, or whether the channel number
determines the interrupting priority.
When this bit is set to 1, it selects the
priority from highest to lowest as follows: REC0, REC1, REC2, ...
TR14, TR15. When this bit is reset to 0,
it selects the priority from highest to lowest as
follows: REC0, TR0, REC1, TR1, REC2, ... REC15, TR15.
Bit 2, Vector Mode Select
This bit selects whether the vector
presented to the 80C186 is a single vector, or 1 of 16
vectors that have the interrupting channel information encoded within
the vector. When this bit is set to 1,
it selects the single vector mode. When this bit is reset to 0,
it selects the multiple vector mode.
Bit 3, Reserved
This bit is reserved.
Bits 4-7, Encoded Channel Number
These bits are read-only, and
are valid only if bit 2 is set to 1 and an interrupt has occurred.
The interrupting channel number is encoded with bit 7 as the MSB
and bit 4 as the LSB.
This register allows all DMA channels to be disabled with one command. The command can take either of two modes, depending on the criticalness of the code path being executed.
The first mode is the write mode. In this mode, a 1 is written to the register to stop all channels, and a 0 is written to restart all channels. There is a possibility that there may be from 1 to 16 pending DMA requests within the DMA/peripheral interface chip at the time the register bit is set to 1 by the I/O write from the 80C186. If any requests are pending, they are serviced immediately, before the code is run. Therefore, critical code paths can be affected.
The second mode is the read mode. In this mode, the executing program must poll the register bit. If it reads a 1 when polled, no internal DMA requests are pending and all subsequent DMA requests are disabled; the critical code will run uninterrupted by DMA activity. All channels are re-enabled by writing a 0 back to the register. If it reads a 0 when polled, 1 or more internal DMA requests are pending, and no channel disabling action is taken. The register must be re-polled if channel disabling is still required.
For either the write or the read mode, the disabled state of the channels is not reflected in the ENABLE/DISABLE bit of the CCW. DMADISABLE is an 8-bit read/write register at I/O address 8214h.
I/O Addresses
-------------
Co-Processor Adapter
DMADISABLE = 8214h
System Unit = None
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| X | X | X | X | X | X | X | DIS|
+----+----+----+----+----+----+----+----+
Bit 0, DIS
This bit is essentially a writable status bit.
If this bit is set to 1, all channels are stopped.
If this bit is reset to 0, all channels are re-enabled.
If this bit is read as a 1, no internal DMA requests are
pending and all channels are stopped.
If this bit is read as a 0, from 1 to 16 DMA
requests are pending internally and no disabling action is taken.
Bits 1-7, Reserved
Always read these bits as 0s.
Each DMA channel has a DMA status register (DMASTAT) associated with it. This register is cleared when it is read. Also, the physical interrupt line is reset by this read. Since three conditions can cause the interrupt, it is possible for multiple conditions to be present when the status register is read. However, since the register and interrupt line are cleared by the read, only one interrupt is presented to the 80C186. Therefore, the interrupt service routine must be capable of servicing all of the possible interrupt sources. Also, the 80C186 EOI command should not be issued until after the status register is read.
I/O Addresses
-------------
Co-Processor Adapter
DMASTAT = 8200h, 820Fh
System Unit = None
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| XX | XX | XX | XX | XX | EM | TC | CM |
+----+----+----+----+----+----+----+----+
Bit 0, Character Match Status
When this bit is set to 1,
it indicates that a character match of the type specified
in CCW bits 8 and 9 has occurred since the last read of the DMASTAT.
Bit 2, End-Of-Message Status
When this bit is set to 1, it indicates that
an end-message condition has occurred
in the DUSCC since the last read of the DMASTAT.
This bit is reset to 0 if these interrupts are disabled in the CCW.
If this bit is set to 1,
an ECHOEOI command to the appropriate command port must precede the
80C186 EOI.
Bit 1, Terminal Count Status
When this bit is set to 1, it indicates
a 0001h-to-0000h transition of the CDT
TCR has taken place since the last read of the DMASTAT.
This bit is set even if these interrupts are disabled in the CCW.
Bits 3-7
These bits are don't care.
See "DMA Subsystem 80C186" for detailed information.
This register is accessed during an 80C186 interrupt acknowledge cycle. It places the 8-bit vector on the bus that the 80C186 uses to point to the address in memory of an interrupt subroutine. Depending upon the vector mode that is programmed in the DMAASSIGN register, this vector either: (1) includes the DMA channel number of the interrupt, or (2) passes back a fixed value. For case (2), the interrupt subroutine then reads the upper four bits of the DMAASIGN register to determine the interrupting DMA channel.
I/O Addresses
-------------
Co-Processor Adapter
DMAVECTOR = 8210h
System Unit = None
Bit 7 6 5 4 3 2 1 0
+----+----+----+----+----+----+----+----+
| VB7| VB6| VB5| VB4| VB3| VB2| VB1| VB0|
+----+----+----+----+----+----+----+----+
Note: This register is a 4-bit I/O write register at 8210h and a 4-bit I/O read register at 8210h. Only VB7, VB6, VB5, and VB0 are read and write. VB1-VB4 are defined only during the interrupt acknowledge cycle of the 80C186.
The interrupt priority logic ensures that the correct vector is supplied for the highest priority pending interrupt.
Bits 0 and 5-7
These bits are programmed at initialization to a base vector value.
This means that the register can supply
any 16 consecutive even-valued vectors or 16
consecutive odd-valued vectors,
if the "in" vector includes the status mode.
Bits 1-4
If the "in" vector includes the status mode,
these bits are set by hardware, and are binary encoded to supply
the DMA channel number of the interrupt source. For example:
4 3 2 1 Channel
+--+--+--+--+--------+
| 0| 0| 0| 0| 0 |
+--+--+--+--+--------+
| 0| 0| 0| 1| 1 |
+--+--+--+--+--------+
| 1| 1| 1| 1| 15 |
+--+--+--+--+--------+
In single-vector mode, these bits are part of the single base vector.
This section describes in detail the commands contained within the DMA/peripheral interface chip.
The DMA/peripheral interface chip acts as the interrupt arbiter for all DUSCC0-3 and CIO0-1 interrupts. This chip contains six command ports that are used to re-enable interrupts within the chip for the 80C186 that may be pending from DUSCC0 or CIO0.
During the interrupt subroutine, the user must do a byte I/O write to the appropriate command port to re-enable interrupts from that particular DUSCC or CIO device. The data is don't care. The I/O write to the particular DMAEOI command port must be at least two instructions after the write to the appropriate DUSCC status register that clears the interrupt. Both writes must be before the 80C186 EOI is issued.
The addresses for the particular DMAEOI command ports are as follows:
Figure 40. DMAEOI Command Port Addresses
+---------------+-------------+ | Particular | I/O Address | | DMAEOI | (hex) | +---------------+-------------+ | DUSCC0 EOI | 3220 | | DUSCC1 EOI | 3221 | | DUSCC2 EOI | 3222 | | DUSCC3 EOI | 3223 | | CIO0 EOI | 3224 | | CIO1 EOI | 3225 | +---------------+-------------+
The co-processor adapter uses a one-byte ID for the interface boards at either address 86h or 0E000h. If an ID already exists at 86h (a non-FFh value), it is assumed that no interface board read-only storage (ROS) exists for this interface board.
The DB I/O CS command provides the interface board with a decode signal that is active in the 80C186 I/O address range from F000h to FFFFh.
Note:
The 80C186 uses the addresses from FF00h to FFFFh. All interface designs using this signal must block any decodes in this range.
This section describes the registers that are addressable by the system unit A number of these registers are contained within the RAM controller and bus master interface chip. Rather than duplicate these registers in this appendix, a reference is made to the appropriate page in Chapter 2 where detailed register information is located.
System-unit addressable registers that are not described elsewhere in this manual are covered in detail in this appendix.
All registers are byte read and write, unless otherwise noted. All unused addresses should be considered as reserved. Bits are described with bit 0 being the least significant bit.
Both power-up reset and command reset values are shown in the "reset condition" section of each register. In these sections, bits shown with "U" represent an undefined or unpredictable state after power-up or reset commands. Bits which are designated with "S" remain in the same state as before the reset command.
+-------------+----------------+----------------+-------------------------+ | Register/ | System Unit | Co-Processor | Detailed Information | | Command | Address (hex) | Adapter | (Page No.) | | Name | (see Note) | Address (hex) | | +-------------+----------------+----------------+-------------------------+ | COMREG | 06 | - | the appropriate section | +-------------+----------------+----------------+-------------------------+ | CAD EN | (15h) | - | the appropriate section | +-------------+----------------+----------------+-------------------------+ | CPUPG | 05 | 14 or 5E | reference #16 | +-------------+----------------+----------------+-------------------------+ | DMAPG | (20)-(3C) | 40 - 5C | reference #17 | +-------------+----------------+----------------+-------------------------+ | DREG | 03 | - | the appropriate section | +-------------+----------------+----------------+-------------------------+ | GAID | (0F) | 18 | reference #18 | +-------------+----------------+----------------+-------------------------+ | INITREG0-3 | (12,10,08,13) | 04,06,-,1A | reference #19 | +-------------+----------------+----------------+-------------------------+ | LOCREG0, 1 | 00, 01 | 00, 02 | reference #23 | +-------------+----------------+----------------+-------------------------+ | PCCSTAT | (14) | 8A | reference #26 | +-------------+----------------+----------------+-------------------------+ | PCPAR0 | (0A,0B,11) | 96, 98, 9A | reference #27 | +-------------+----------------+----------------+-------------------------+ | PROCSYNC | 07 | 8E | reference #29 | +-------------+----------------+----------------+-------------------------+ | PTRREG | 02 | - | the appropriate section | +-------------+----------------+----------------+-------------------------+ | TREG | 04 | 12 or 16 | reference #31 | +-------------+----------------+----------------+-------------------------+ | INTCOM | 02 | - | the appropriate section | +-------------+----------------+----------------+-------------------------+ | INTCOM ALT | 02 | - | the appropriate section | +-------------+----------------+----------------+-------------------------+Note:
Values given in parentheses are pointer register values. All other values are offsets and should be added to the base address value programmed in INITREG0.
The COMREG register is a system unit read/write register. Its purpose is to provide some control over the co-processor adapter from the system unit's microprocessor.
I/O Addresses
-------------
System Unit = Base + 0006h
Co-Processor Adapter = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ COMREG
| | | | | | | |
| | | | | | | +----- RC
| | | | | | +-------- NC
| | | | | +----------- DG
| | | | +-------------- FP
| | | +----------------- IE
| | +-------------------- IP
| +----------------------- 0
+-------------------------- 0
Bit 0, Reset Command
Setting this bit to 1 causes a partial RAM controller and bus master interface chip reset, and a
hardware reset of the co-processor adapter. The co-processor adapter is held in
reset until this bit is reset to 0.
This command should be issued for a least one microsecond.
Before issuing this command, the user may want to clear
the "PROM ready" bit to know when the PROM POST is finished,
as with a power-up reset.
The following registers are affected:
Register After Reset Command
+------+ +-----------------+
COMREG 0000 0000
NMIMASK 0011 1111
NMISTAT 0000 0000
TREG 1111 1111
The following also are reset to zero:
Example: COMREG data = 0000 0001 and it is desired
to clear the reset command (bit 0) to 0
and set the NMI (bit 1) to 1:
Incorrect: System unit write COMREG data = 0000 0010
Correct: System unit write COMREG data = 0000 0000
(first)
System unit write COMREG data = 0000 0010
(second)
Bit 2, Degate RAM
Caution should be exercised when using this bit. Undetermined behavior of the RAM controller and bus master interface chip will occur if this bit is set during a system unit memory read or memory write cycle.
Figure 41. COMREG Bit 2 Description
System Unit System Unit
Write -----------+ Read -------------+
| | System Unit
System Unit +--+--+ +--+---+ Data Bit
Data Bit | | +----+ | | (DG)
(DG) ---->|Latch+--->| | +--->|Buffer+--------->
| | | | | | |
+-----+ | | DG Internal | +------+
| | Control Bit |
| OR +-------------+ Co-Processor
Co-Processor | | | Adapter
Adapter +-----+ | | | +------+ Data Bit
Data Bit | | | | | | | (DG)
(DG) ---->|Latch+--->| | +--->|Buffer+--------->
| | +----+ | |
Co-Processor +--+--+ Co-Processor +--+---+
Adapter | Adapter |
Write -----------+ Read -------------+
IF . . . THEN . . .
+-----------------------------+ +----------------------------+
| System Unit AND Co-Proc | | System Unit AND Co-Proc|
| Writes Writes | | Reads Reads |
+-----------------------------+ +----------------------------+
| 0 & 0 | | 0 & 0 |
| 0 & 1 | | 1 & 1 |
| 1 & 0 | | 1 & 1 |
| 1 & 1 | | 1 & 1 |
+-----------------------------+ +----------------------------+
Bit 3, Force Bad Parity
System Unit System Unit
Write -----------+ Read -------------+
| | System Unit
System Unit +--+--+ +--+---+ Data Bit
Data Bit | | +----+ | | (FP)
(FP) ---->|Latch+--->| | +--->|Buffer+--------->
| | | | | | |
+-----+ | | FP Internal | +------+
| | Control Bit |
| OR +-------------+ Co-Proc
Co-Processor | | | Adapter
Adapter +-----+ | | | +------+ Data Bit
Data Bit | | | | | | | (FP)
(FP) ---->|Latch+--->| | +--->|Buffer+--------->
| | +----+ | |
Co-Processor +--+--+ Co-Processor +--+---+
Adapter | Adapter |
Write -----------+ Read -------------+
IF . . . THEN . . .
+-----------------------------+ +----------------------------+
| System Unit AND Co-Proc | | System Unit AND Co-Proc|
| Writes Writes | | Reads Reads |
+-----------------------------+ +----------------------------+
| 0 & 0 | | 0 & 0 |
| 0 & 1 | | 1 & 1 |
| 1 & 0 | | 1 & 1 |
| 1 & 1 | | 1 & 1 |
+-----------------------------+ +----------------------------+
Bit 4, Interrupt Enable
Bit 5, Interrupt Pending
If an interrupt is pending for the system unit, then IP=1.
This is a read-only bit; it is reset to 0
by reading the TASK register.
This bit also is cleared by a channel reset.
Bit 6, Reserved
Always read as a 0.
Bit 7, Reserved
Always programmed to 0; always read as a 0.
Power-up: 0000 0000
Reset command: 0000 0SS0
The CAD EN register is a system unit write-only register. This register enables the co-processor adapter to detect the Micro Channel bus reset signal going active. Typically, this signal goes active during a control-alt-delete sequence, under program control. Once detected, the co-processor adapter's memory is degated from the Micro Channel, and an NMI is posted to the 80C186, if this NMI is enabled in the NMIMASK. An I/O write from the system unit (any data) enables the detection feature. Once the feature is enabled, it cannot be disabled unless a card reset is performed in the command register, or power is turned off to the system. If enabled, memory always will be degated following a Ctrl-Alt-Delete sequence.
I/O Addresses
-------------
System Unit
CAD EN = Use DREG with PTRREG preset to 0015h
Co-Processor Adapter = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ CAD EN
| | | | | | | |
| | | | | | | +----- D0
| | | | | | +-------- D1
| | | | | +----------- D2
| | | | +-------------- D3
| | | +----------------- D4
| | +-------------------- D5
| +----------------------- D6
+-------------------------- D7
Bits 0-7, Data Bits
These bits are don't care.
Power-up: Disabled
Reset command: Disabled
The system unit DREG register is a pseudo register. It is a window to a variety of registers, only one of which is enabled at a time by the PTRREG register. Read and write characteristics are determined by the characteristics of the register enabled by the PTRREG register.
I/O Addresses
-------------
System Unit
DREG = Base + 0003h
Co-Processor Adapter = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ DREG
| | | | | | | |
| | | | | | | +----- D0
| | | | | | +-------- D1
| | | | | +----------- D2
| | | | +-------------- D3
| | | +----------------- D4
| | +-------------------- D5
| +----------------------- D6
+-------------------------- D7
Bit 0-7, Data Bits
Data is variable, depending on which register
is enabled by the PTRREG register.
Power-up: UUUU UUUU
Reset command: UUUU UUUU
The PTRREG register is a system unit read/write register. It enables other system unit registers to be accessed by the data register. Only one register is enabled at a time, based on the value in the PTRREG register. Once programmed with a value, the enabled register may be accessed multiple times, provided that the PTRREG register is not changed during that time. The individual registers that the PTRREG register accesses are discussed separately.
I/O Addresses
-------------
System Unit
PTRREG = Base + 0002h
Co-Processor Adapter = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++ PTRREG
| | | | | | | |
| | | | | | | +----- R0
| | | | | | +-------- R1
| | | | | +----------- R2
| | | | +-------------- R3
| | | +----------------- R4
| | +-------------------- R5
| +----------------------- R6
+-------------------------- R7
Bits 0-7, Register Value
These bits refer to the value needed in the
PTRREG register to access a particular register through
the DREG register. Reserved registers should not be
used, since the results are unpredictable.
Figure 43.
Figure 43. PTRREG Bits 0-7 Description
+---------+-----------------------++---------+-------------------+ | R0-R7 | Register/Function || R0-R7 | Register/Function | +---------+-----------------------++---------+-------------------+ | (00-07) | Reserved || (20) | DMAPAGE0 | | (08) | INITREG2 || (22) | DMAPAGE1 | | (09) | Reserved for INTCOM || (24) | DMAPAGE2 | | (0A) | PCPAR0 || (26) | DMAPAGE3 | | (0B) | PCPAR1 || (28) | DMAPAGE4 | | (0C) | Reserved || (2A) | DMAPAGE5 | | (0D) | Reserved || (2C) | DMAPAGE6 | | (0E) | Reserved || (2E) | DMAPAGE7 | | (0F) | GAID || (30) | DMAPAGE8 | | (10) | INITREG1 || (32) | DMAPAGE9 | | (11) | PCPAR2 || (34) | DMAPAGE10 | | (12) | INITREG0 || (36) | DMAPAGE11 | | (13) | INITREG3 || (38) | DMAPAGE12 | | (14) | PCCSTAT || (3A) | DMAPAGE13 | | (15) | CAD EN || (3C) | DMAPAGE14 | | (16-1F) | Reserved || (40-4F) | INTCOM ALT | | | || (50-FF) | Reserved | +---------+-----------------------++---------+-------------------+
Power-up: UUUU UUUU
Reset command: UUUU UUUU
This section describes in detail the commands that are addressable by the system unit.
INTCOM is a system unit write-only command. It is used to cause a standard interrupt (INT0 of the 80C186) to the co-processor adapter. A write to this address of the data specified below causes the corresponding bit in the co-processor adapter interrupt identifier register (INTIDREG) to be set to 1. See "Interrupt Identifier Register (INTIDREG)" for further details.
I/O Addresses
-------------
System Unit = Base + 0002h
Co-Processor Adapter = None
+--+--+--+--+--+--+--+--+
|D7|D6|D5|D4|D3|D2|D1|D0|
+-++-++-++-++-++-++-++-++
| | | | | | | |
| | | | | | | +----- IC0
| | | | | | +-------- IC1
| | | | | +----------- IC2
| | | | +-------------- IC3
| | | +----------------- IC4
| | +-------------------- IC5
| +----------------------- IC6
+-------------------------- IC7
Power-up: Not applicable
Reset command: Not applicable
(1) For interface board specifications, refer to the appropriate chapter that describes the interface board.
(2) These voltages are not used on the co-processor adapter card. They are provided for use on the interface board.
(3) For data rates above 1M baud, the polarity of the transmit clock signal should be reversed (that is, interchange the STA signal with the STB signal).
(4) To operate at data rates above 1M baud, the polarity of the transmit clock signal must be reversed.
(5) Designates Realtime Control Microcode routines. (Refer to the IBM Realtime Interface Co-Processor Firmware Technical Reference for information on these routines.)
(6) To support V.35 data rates above 1M baud, the polarity of the transmit clock signal has been reversed (that is, the TXCA and the TXCB lines have been interchanged).
Last modified: March 25, 1999