AMD SUPERNET 2 FDDI chip set.
  Am79C830 - FORMAC Plus - (FDDI MAC layer)
  Am79C864 - PLC-S - FDDI Physical Layer Controller with Scrambler
  Am79865 - PDT - FDDI Physical Data Transmitter (transmit clock chip)
  Am79866 - PDR - FDDI Physical Data Receiver (receive clock chip)
OKI M82C54-2 CMOS PROGRAMMABLE INTERVAL TIMER

LEDs Green and Amber
Green on - Card initialized, SMT running, connected to network. May be problems at higher level protocol layers, but card can communicate with other stations.
Amber on - Card initialized and SMT running, card NOT connected to network. Possibly cable troubles or neighboring station is down.
Green and Amber Off - No board driver has been loaded and SMT not running.

NOTE: When an SK-52xx is used in a 16-bit slot, the SK-52xx can only access the first 16MB of RAM and may not work properly in systems with more memory.

I/O Port Address Location
   Each FDDI adapter installed is assigned a unique address location.
    <"0200-03ff">, 0600-07ff, 0a00-0bff, 1200-13ff, 2200-23ff, 4200-43ff, 8200-83ff, fe00-ffff, fa00-fbff, f600-f7ff, ee00-efff, de00-dfff, be00-bfff, 7e00-7fff

Interrupt Level
   This adapter can operate on one of four interrupt levels: 3, 9, 10, or 11
    <"Interrupt 9">, 10, 11, 3

EPROM Address location
   There are 7 possible 16K blocks of PC memory that can be assigned for accessing the EPROM area of the FDDI Network adapter.
    <"EPROM Disabled">, C4000-C7FFF, C8000-CBFFF, CC000-CFFFF, D0000-D3FFF, D4000-D7FFF, D8000-DBFFF, DC000-DFFFF

Remote boot on/off
   Enables/disables booting from network.
     <"Remote boot on">, Remote boot off

Bus Master Arbitration Level
   Each Busmaster and/or DMA device is assigned an  unique arbitration level in order to arbitrate conflicting requests.
    <"Level 8">, 9, 10, 11, 12, 13, 14

Fairness on/off
   Each participant is assigned a priority by arbitration level .
      Fairness on:  Priority defines sequence of granting the bus on conflicting requests. The latency time on bus requests is calculable.
     Fairness off: Higher priority gives more time on the bus.  The latency time on bus requests is NOT calculable.
     <"Fairness ON">, Fairness OFF

Streaming data enable/disable
     <"Streaming data disable>, Streaming data enable

Check on forbidden 8-Bit accesses
   Working as busmaster the adapter supports accesses to 32-Bit and 16-Bit memory slaves. If the adapter performs an access to an 8-Bit slave an interrupt may be asserted and reported (check on) or not (check off).
    <"Check on">, Check off

Check CHCK
   Working as busmaster the adapter may check the control line 'CHCK'. If the check is enabled the adapter asserts an interrupt and reports this event.
   <"Check on">, Check off