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AX = B10Ah subfn 1045h BH = bus number BL = device/function number (bits 7-3 device, bits 2-0 function) DI = register number (0000h-00FFh) (see #00878)
Return:
CF clear if successful ECX = dword read CF set on error AH = status (00h,87h) (see #00729) EAX, EBX, ECX, and EDX may be modified all other flags (except IF) may be modified
Notes: This function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call. The meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation
See Also: AX=B10Ah - AX=B10Ah/SF=1042h - AX=B10Ah/SF=1066h
Format of PCI Configuration data for OPTi 82C750 Vendetta (device 0): Offset Size Description (Table 00929) 00h 64 BYTEs header (see #00878) (vendor ID 1045h, device ID C567h) 40h DWORD memory control (see #00930) 44h 6 BYTEs data path control (see #00931) 4Ah WORD reserved 4Ch BYTE SDRAM SDRAS/SDCAS mux control (see #00932) 4Dh BYTE SDRAM select (see #00933) 4Eh BYTE ECC test / I2C control (see #00934) 4Fh BYTE ECC test data 50h DWORD ECC control (see #00935) 54h WORD SDRAM select (see #00936) 56h BYTE data path control / EDO X-2-2-2 writes (see #00937) 57h BYTE reserved 58h DWORD ECC reporting (see #00938) 5Ch 164 BYTEs reserved
See Also: #00878 - #00939 - #00965
Bitfields for OPTi 82C750 Vendetta (device 0) memory control: Bit(s) Description (Table 00930) 31-30 reserved 29 reserved (1) 28-18 reserved 17 reserved (1) 16 HA drive-back during CPU memory access enable 15-6 PCI video frame buffer write posting hole 5-4 reserved 3 PCI bus write post disable 2 video frame buffer write post (posting enabled if bit 2 = bit 3) 1 video memory write post(posting enabled if bit 1 = bit 3) 0 I/O cycle write post enable
See Also: #00929 - #00931
Bitfields for OPTi 82C750 Vendetta (device 0) data path control: Bit(s) Description (Table 00931) 41-47 reserved 40 DTY pin suspend enable 39-38 reserved 37 SDRAM refresh 0 sized bank RAS# disable 36 SDRAM control signal stepping enable 35 reserved 34-32 SDRAM mode. 000 = normal. 001 = NOP enable. 010 = precharge all banks. 011 = mode register enable. 100 = CBR cycle enable. 101-111 = reserved 31 SDRAM memory read access enable 30 CPU-to-PCI FIFO clear enable 29 PCI-to-DRAM FIFO clear enable 28 CPU-to-DRAM FIFO clear enable 27 82C750 register write disable 26-15 reserved 14 PCI master/ECC generate NMI disable 13-12 reserved (1) 11 memory parity checking enable 10 reserved 9 CPU DRAM write byte merge enable 8 MD bus pull-up resistor disable 7 PCI CPU write 6DW FIFO enable 6 DRAM PCI read 24DW FIFO enable 5 DRAM PCI write 24DW FIFO enable 4 DRAM CPU write 8QW FIFO enable 3 82C750 memory read access (0 = SDRAM, 1 = reserved) 2-1 reserved 0 82C750 memory read access (0 = FP mode, 1 = EDO/SDRAM)
See Also: #00929
Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM SDRAS/SDCAS mux control: Bit(s) Description (Table 00932) 7 MCACHE enable 6 GWE#/BWE# (1) 5 reserved (read-only) 4 reserved (1) 3 BOFF# CPU status latch enable 2 reserved (1) (SDRAS# & SDCAS#) 1 reserved (1) (BA1 & BA0) 0 pin mux. 0 = RAS4# & RAS5#. 1 = SDRAS# & SDCAS#
See Also: #00929
Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM select: Bit(s) Description (Table 00933) 7-6 reserved 5 bank 5 enable 4 bank 4 enable 3-0 reserved
See Also: #00929
Bitfields for OPTi 82C750 Vendetta (device 0) ECC test / I2C control: Bit(s) Description (Table 00934) 7 ECC test mode enable 6 reserved 5 reserved (1 if SDRAM enabled) 4 I2C data output read-back (read-only) 3 I2C clock output read-back (read-only) 2 I2C data output (refer to file I2C.LST for more details) 1 I2C clock output 0 I2C control enable
See Also: #00929 - I2C A0h - #00935
Bitfields for OPTi 82C750 Vendetta (device 0) ECC control: Bit(s) Description (Table 00935) 31-13 upper 19 bits of error address 12-5 syndrome byte for reported error 4 non-correctable error 3 single-bit error 2 nibble error 1 ECC error report enable 0 ECC data path enable
See Also: #00929 - #00934
Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM select: Bit(s) Description (Table 00936) 15 SDWE# stepping enable 14 reserved (1) (SDRAM) 13-12 reserved 11-6 bank 5-0 SDRAM technology. 0 = 16 Mb. 1 = 64 Mb 5-0 bank 5-0 SDRAM timing. 0 = leadoff 7/6. 1 = leadoff 8/7
See Also: #00929
Bitfields for OPTi 82C750 Vendetta (device 0) data path control / EDO X-2-2-2: Bit(s) Description (Table 00937) 7 CPU-to-DRAM FIFO enable 6 1 CLK CAS enable 5-0 RAS5#-RAS0# X-2-2-2 write enable. (CPU-to-DRAM FIFO, DRAM write post, and cache readaround write must be enabled)
See Also: #00929
Bitfields for OPTi 82C750 Vendetta (device 0) ECC reporting: Bit(s) Description (Table 00938) 31-26 reserved 25-16 single-bit error counter 15 reserved 14 delayed write enable 13-4 single-bit error limit 3 correctable error reporting (0 = NMI, 1 = SMI) 2 single-bit error counter enable (disabling resets counter) 1 error reporting method (0 = NMI, 1 = SMI) 0 NMI/SMI generate disable
See Also: #00929
Format of PCI Configuration data for OPTi 82C750 Vendetta (device 1): Offset Size Description (Table 00939) 00h 64 BYTEs header (see #00824) (vendor ID 1045h, device ID C568h) 40h WORD keyboard control (see #00940) 42h WORD interrupt control (see #00941) 44h BYTE pin functionality 1 (see #00942) 45h BYTE reserved 46h WORD cycle control (see #00943) 48h WORD pin functionality 2 (see #00944) 4Ah WORD ROMCS# range control (see #00945) 4Ch BYTE miscellaneous control 1 (see #00946) 4Dh BYTE reserved 4Eh BYTE miscellaneous control 2 (see #00947) 4Fh BYTE miscellaneous control 3 (see #00948) 50h WORD interrupt trigger control (see #00949) 52h WORD interrupt multiplexing control (see #00950) 54h WORD PCI master control (see #00951) 56h WORD serial interrupt source (see #00952) 58h BYTE serial interrupt mode control (see #00953) 59h BYTE pin functionality 3 (see #00954) 5Ah WORD distributed DMA master base address 5Ch BYTE distributed DMA control (see #00955) 5Dh 3 BYTEs reserved 60h BYTE USB interrupt control register (see #00956) 61h BYTE PCI reset control (see #00957) 62h BYTE emulation control (see #00958) 63h BYTE PCI retry control (see #00959) 64h 153 BYTEs reserved FDh BYTE SMI control FEh BYTE stop grant cycle control FFh BYTE host memory parity error
See Also: #00878 - #00929 - #00965
Bitfields for OPTi 82C750 Vendetta (device 1) keyboard control: Bit(s) Description (Table 00940) 15 keyboard port read (read-only) 14 keyboard port write (read-only) 13 keyboard RESET CPUINIT. 0 = generate immediately. 1 = wait for halt 12 keyboard emulation disable 11-9 PIRQ3# IRQ generation. 000 = use interrupt trigger control register (offset 50h). 001 = IRQ5. 010-101 = IRQ9-IRQ12. 110-111 = IRQ14-IRQ15 8-6 PIRQ2# IRQ generation 5-3 PIRQ1# IRQ generation 2-0 PIRQ0# IRQ generation
See Also: #00939 - #00941
Bitfields for OPTi 82C750 Vendetta (device 1) interrupt control: Bit(s) Description (Table 00941) 15 ISA IRQ14 blocking enable 14 ISA IRQ15 blocking enable 13 DMA/ISA master to preempt PCI master enable 12 PCI priority is fixed instead of rotating 11-10 back-to-back ISA I/O delay. 00 = 3 ATCLKs. 01 = 12 ATCLKs. 10 = no delay. 11 = delay all by 12 ATCLKs 9 PCI master ISA device access disable 8 ISA bus control signals for memory access >16M and I/O access >64K disable 7-6 IRQ15-IRQ14 triggering (0 = edge, 1 = level) 5-2 IRQ12-IRQ9 triggering (0 = edge, 1 = level) 1 IRQ 5 triggering (0 = edge, 1 = level) 0 pin AE16 functionality. 0 = DREQ6. 1 = EPMI0#
See Also: #00939 - #00940
Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 1: Bit(s) Description (Table 00942) 7-6 pin AC15 functionality. 00-01 = controlled by bits 1-0. 10 = DACK7#. 11 = reserved 5-4 pin AE15 functionality. 00-01 = controlled by bits 1-0. 10 = DACK6#. 11 = reserved 3-2 pin AF15 functionality. 00-01 = controlled by bits 1-0. 10 = DACK5#. 11 = reserved 1-0 DACK group-wise programmable pin functionalities. 00 = DACK3#-DACK0#. 01 = DACK7#-DACK5#, DACK3#, DACK1#, DACK0#. 10 = reserved. 11 = EDACK2#-EDACK0#, EDACKEN#, PIRQ3#, PIRQ2#
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) cycle control: Bit(s) Description (Table 00943) 15 ISA bus ROM write enable 14 hidden refresh enable 13-12 ATCLK select. 00 = LCLK/4. 01 = LCLK/3. 10 = LCLK/2. 11 = LCLK 11 CPU master to PCI slave write. 0 = 1 LCLK. 1 = 0 LCLK 10-8 PCI master to PCI master preempt timer. 000 = no preempt. 001 = 260 LCLKs. 010 = 132 LCLKs. 011 = 68 LCLKs. 100 = 36 LCLKs. 101 = 20 LCLKs. 110 = 12 LCLKs. 111 = 5 LCLKs 7 reserved 6 XDIR achieve. 0 = accessing ROM, keyboard controller, RTC. 1 = accessing ROM, NVRAM 5 PERR# to SERR# conversion enable 4 address parity checking enable 3 target abort SERR# generation enable 2 fast back-to-back enable 1 sample point decoding. 0 = slow. 1 = subtractive 0 reserved
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 2: Bit(s) Description (Table 00944) 15 pin AF18 functionality (0 = IRQ15, 1 = reserved) 14-13 pin AE19 functionality (00-01 = IRQ12, 10-11 = reserved) 12 pin AD20 functionality (0 = IRQ10, 1 = MIRQ10/12) 11 pin AE21 functionality (0 = IRQ6, 1 = reserved) 10 pin AD22 functionality (0 = IRQ4, 1 = MIRQ4/6) 9-8 pin AD16 functionality (00 = DREQ7, 01 = EPMI3#, 1x = reserved) 7-6 pin AD17 functionality. 00 = DREQ3. 01 = DREQ3/7. 10 = DREQ7. 11 = reserved 5-4 pin AD18 functionality. 00 = DREQ1. 01 = DREQ1/6. 10 = DREQ6. 11 = reserved 3-2 pin AE18 functionality. 00 = DREQ0. 01 = DREQ0/5. 10 = DREQ5. 11 = reserved 1-0 pin T23 functionality (0x = PREQ1#, 1x = reserved)
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) ROMCS# range control: Bit(s) Description (Table 00945) 15 FFFF8000h-FFFFFFFFh ROMCS# disable 14 FFFF0000h-FFFF7FFFh ROMCS# disable 13 FFFE8000h-FFFEFFFFh ROMCS# enable 12 FFFE0000h-FFFE7FFFh ROMCS# enable 11 FFFD8000h-FFFDFFFFh ROMCS# enable 10 FFFD0000h-FFFD7FFFh ROMCS# enable 9 FFFC8000h-FFFCFFFFh ROMCS# enable 8 FFFC0000h-FFFC7FFFh ROMCS# enable 7 F8000h-FFFFFh ROMCS# disable 6 F0000h-F7FFFh ROMCS# disable 5 E8000h-EFFFFh ROMCS# enable 4 E0000h-E7FFFh ROMCS# enable 3 D8000h-DFFFFh ROMCS# enable 2 D0000h-D7FFFh ROMCS# enable 1 C8000h-CFFFFh ROMCS# enable 0 C0000h-C7FFFh ROMCS# enable
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 1: Bit(s) Description (Table 00946) 7-5 reserved 4 game port/MPU-401 enable 3 PREQ4#/PGNT4# mux (0 = SDA2/GP3, 1 = PREQ4#/PGNT4#) 2 DACK5# 1-to-0 transition enable 1-0 reserved
See Also: #00939 - #00947 - #00948
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 2: Bit(s) Description (Table 00947) 7-4 reserved 3 pipeline byte merge enable 2 EOP configuration (0 = output, 1 = input) 1 byte merge enable 0 ISA master data swap disable
See Also: #00939 - #00946 - #00948
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 3: Bit(s) Description (Table 00948) 7 pin AB15 functionality. 0 = DACK5#. 1 = PPWRL+PPWRL2 6 IDE functionality support enable 5 reserved (read-only) 4 ISA bus AT command 1 wait state extension disable 3-2 reserved 1 pin AE14 functionality. 0 = controlled by offset 44h bits 1-0. 1 = GPCS2# 0 reserved
See Also: #00939 - #00946 - #00947
Bitfields for OPTi 82C750 Vendetta (device 1) interrupt trigger control: Bit(s) Description (Table 00949) 15 reserved (1) 14 reserved 13 pin AD15 functionality (0 = DACK2#, 1 = GPCS2#) 12-11 reserved 10 IRQ3 triggering (0 = edge, 1 = level) 9 IRQ4 triggering (0 = edge, 1 = level) 8 IRQ7 triggering (0 = edge, 1 = level) 7-6 IRQ generation when PIRQ3# triggered. 00 = disable. 01 = IRQ3. 10 = IRQ4. 11 = IRQ7 5-4 IRQ generation when PIRQ2# triggered. 00 = disable. 01 = IRQ3. 10 = IRQ4. 11 = IRQ7 3-2 IRQ generation when PIRQ1# triggered. 00 = disable. 01 = IRQ3. 10 = IRQ4. 11 = IRQ7 1-0 IRQ generation when PIRQ0# triggered. 00 = disable. 01 = IRQ3. 10 = IRQ4. 11 = IRQ7
See Also: #00939 - #00950
Bitfields for OPTi 82C750 Vendetta (device 1) interrupt multiplexing control: Bit(s) Description (Table 00950) 15 pin functionality. 0 = AE22:IRQ3, AF21:IRQ5, AE21:IRQ6, AD21:IRQ7, AE20:IRQ9, AF19:IRQ11. 1 = AE22:MIRQ3/5, AF21:MIRQ7/9, AE21:MIRQ11/15, AD21:EPMI1#, AE20:EPMI2#, AF19:GMIRQ 14 pin R22 functionality (0 = PREQ2#, 1 = EPMI0#) 13 IRQ1 latching enable 12 IRQ12 latching enable 11 DACKEN# status (0 = active low, 1 = active high) 10 system bus owned by external device 9 flash ROM locking enable 8 reserved 7 IRQ6 triggering (0 = edge, 1 = level) 6-3 IRQ generation when GMIRQ triggered. 0000 = disabled. 0001-0010 = reserved. 0011-0111 = IRQ3-IRQ7. 1000 = reserved. 1001-1100 = IRQ9-IRQ12. 1101 = reserved. 1110-1111 = IRQ14-IRQ15 2 reserved (1) 1 priority scheme enable 0 concurrent refresh and IDE cycle enable
See Also: #00939 - #00949
Bitfields for OPTi 82C750 Vendetta (device 1) PCI master control: Bit(s) Description (Table 00951) 15-12 reserved 11 interrupt request register recover enable 10 DMA address and counter (0 = current, 1 = base) 9 CPU/PCI master access ISA cycle retry enable 8 CPU-to-PCI cycle AHOLD signal use enable. (used only when bit 4 = 1) 7 PCI master X-1-1-1 write enable 6 PCI master X-1-1-1 read enable 5 concurrent PCI master/IDE enable 4 new AHOLD protocol enable 3 PCI master non-contiguous byte enable 2 reserved 1 simultaneous hardware PMU and IDE function operation enable 0 ISA refresh disable
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) serial interrupt source: Bit(s) Description (Table 00952) 15-3 IRQ15-IRQ3 interrupt resource (0 = ISA, 1 = serial interrupt) 2 SMI#, IOCHK#, PCIRQ3#-PCIRQ0# interrupt resource. 0 = ISA. 1 = serial interrupt 1-0 IRQ1-IRQ0 interrupt resource (0 = ISA, 1 = serial interrupt)
See Also: #00939 - #00953
Bitfields for OPTi 82C750 Vendetta (device 1) serial interrupt mode control: Bit(s) Description (Table 00953) 7-6 serial interrupt control mode. 00 = continuous. 01 = idle. 1x = active 5 reserved 4 data frame slot support. 0 = 17 slots (IRQ15-IRQ3, IRQ1-IRQ0, SMI#, IOCHK#). 1 = 21 slots (IRQ15-IRQ3, IRQ1-IRQ0, SMI#, IOCHK#, PCIRQ3#-PCIRQ0#) 3-2 CPU access PCI priority. 00 = lowest. 01 = higher after 4 PCI master grants. 10 = higher after 2 PCI master grants. 11 = higher after 3 PCI master grants 1-0 serial interrupt start frame pulse width in continuous/active mode. 00 = 4/3 CLK. 01 = 6/5 CLK. 10 = 8/7 CLK. 11 = reserved
See Also: #00939 - #00952
Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 3: Bit(s) Description (Table 00954) 7 PCI arbitration time-out mode enable 6 0 wait state for CPU I/O access enable 5 SMI output disable 4 CPU request for PCI bus (0 = enabled, 1 = reserved) 3 reserved 2 refresh preemption disable 1-0 reserved
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) distributed DMA control: Bit(s) Description (Table 00955) 7-5 channel 7-5 enable 4-1 channel 3-0 enable 0 DDMA enable
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) USB interrupt control register: Bit(s) Description (Table 00956) 7 reserved 6-5 buffered DMA control. 00 = original DMA with old protocol. 01 = reserved. 10 = original DMA with PCI master capability. 11 = buffered DMA enable 4 reserved 3-0 IRQ generation when USBIRQ triggered. 0000 = disabled. 0001-0010 = reserved. 0011-0111 = IRQ3-IRQ7. 1000 = reserved. 1001-1100 = IRQ9-IRQ12. 1101 = reserved. 1110-1111 = IRQ14-IRQ15
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) PCI reset control: Bit(s) Description (Table 00957) 7 PCI soft reset generate enable 6 PCI slave demand mode buffered DMA retry fix enable 5 IORDY# PCI master delay fix enable 4 ISA command deassertion IOCHRDY delay. 0 = <1 ATCLK. 1 = >=1 ATCLK 3-2 buffered DMA fix (00 = disable, 11 = enable) 1 reserved 0 ISA master synchronization (1)
See Also: #00939
Bitfields for OPTi 82C750 Vendetta (device 1) emulation control: Bit(s) Description (Table 00958) 7 PCIRST# disable 6 SDA2 muxed with XDIR (0 = XDIR, 1 = SDA2) 5 SPKR muxed with MIDI1 (0 = MIDI1, 1 = SPKR) 4 audio mux (0 = MP7-MP0, DACK) 3 audio module enable 2 ATA-33 IDE pin mux scheme (0 = old, 1 = new) 1 REFRESH priority (0 = high, 1 = lowest) 0 port 92h emulation disable
See Also: #00939 - PORT 0092h
Bitfields for OPTi 82C750 Vendetta (device 1) PCI retry control: Bit(s) Description (Table 00959) 7-2 reserved 1 reserved (1) 0 ISA slave PCI master retry. 0 = no change. 1 = generate BOFF#
See Also: #00939
Format of PCI Configuration data for OPTi 82C750 Vendetta (IDE controller): Offset Size Description (Table 00960) 00h 64 BYTEs header (see #00824) (vendor ID 1045h, device ID C621h) 40h BYTE IDE initialization control (see #00961) 41h BYTE reserved 42h BYTE IDE enhanced feature (see #00962) 43h BYTE IDE enhanced mode (see #00963) 44h WORD ultra DMA mode select (see #00964) 46h 186 BYTEs reserved
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE initialization control: Bit(s) Description (Table 00961) 7-6 bus master IDE PCI bus request when FIFO filled with. 00 = 32 bytes (early request disabled). 01 = 30 bytes. 10 = 28 bytes. 11 = 26 bytes 5 reserved (1) 4 reserved 3 secondary IDE disable 2 I/O addresses relocatable 1-0 IDE device default cycle time. 00 = >=600ns (PIO mode 0). 01 = >=383ns (PIO mode 2). 10 = >=240ns (PIO mode 1). 11 = >=180ns (PIO mode 3)
See Also: #00960
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE enhanced feature: Bit(s) Description (Table 00962) 7 reserved 6 IDE write concurrency enable 5 slave IDE FIFO to ISA bus preemption disable 4 IDE arbiter PCI/IDE concurrency support enable 3 PCI memory commands enable 2 PCI master IDE and IDE cycle concurrency enable 1 PCI master X-1-1-1 MIDE enable 0 reserved
See Also: #00960 - #00963
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE enhanced mode: Bit(s) Description (Table 00963) 7-6 secondary IDE drive 1 enhanced mode. 00 = disabled. 01 = command recovery in 1 LCLK. 10 = command recovery in 0 LCLK. 11 = reserved 5-4 secondary IDE drive 0 enhanced mode. 00 = disabled. 01 = command recovery in 1 LCLK. 10 = command recovery in 0 LCLK. 11 = reserved 3-2 primary IDE drive 1 enhanced mode. 00 = disabled. 01 = command recovery in 1 LCLK. 10 = command recovery in 0 LCLK. 11 = reserved 1-0 primary IDE drive 0 enhanced mode. 00 = disabled. 01 = command recovery in 1 LCLK. 10 = command recovery in 0 LCLK. 11 = reserved
See Also: #00960 - #00963
Bitfields for OPTi 82C750 Vendetta (IDE Controller) ultra DMA mode select: Bit(s) Description (Table 00964) 15 primary IDE disable 14-12 reserved 11-10 secondary IDE drive 1 ultra DMA mode. 00 = mode 0. 01 = mode 1. 10 = mode 2. 11 = reserved 9-8 secondary IDE drive 0 ultra DMA mode (same values as bits 11-10) 7-6 primary IDE drive 1 ultra DMA mode (same values as bits 11-10) 5-4 primary IDE drive 0 ultra DMA mode (same values as bits 11-10) 3 secondary IDE drive 1 ultra DMA 33 enable 2 secondary IDE drive 0 ultra DMA 33 enable 1 primary IDE drive 1 ultra DMA 33 enable 0 primary IDE drive 0 ultra DMA 33 enable
See Also: #00960
Format of PCI Configuration data for OPTi 82C861/82C871 PCI-to-USB Bus Bridge: Offset Size Description (Table 00965) 00h 64 BYTEs header (see #00878) (vendor ID 1045h, device ID C861h) 40h 4 BYTEs reserved for testing 44h 10 BYTEs reserved 4Eh BYTE I2C control
bits 7-5:
Reservedbit 4:
I2C data output read-back (read-only)bit 3:
I2C clock output read-back (read-only)bit 2:
I2C data outputbit 1:
I2C clock outputbit 0:
I2C control enable 4Fh BYTE reserved 50h BYTE PCI host feature controlbits 7-4:
Reservedbit 3:
Subsystem vendor ID register write disablebit 2:
CLKRUN# enablebit 1:
Port 2 output disablebit 0:
Port 1 output disable 51h BYTE interrupt assignmentbit 7:
Host controller type 0 = Viper-N+ (send 1 data phase on IRQ driveback) 1 = FireStar (send 2 data phases on IRQ driveback)bit 6:
IRQ driveback enablebit 5:
Reservedbits 4-0:
Interrupt assignment 00000 = disabled 00001 = PCIRQ0# (default) to 00100 = PCIRQ3#, 00101 = ACPI0 to 01111 = ACPI10 10000 = IRQ0 to 11111 = IRQ15 52h 2 BYTEs reserved 54h DWORD IRQ driveback addressbits 1-0:
Reserved to 00 (read-only) 58h 20 BYTEs reserved 6Ch DWORD reserved (test mode enable)
See Also: #00878 - #00929 - #00939
Format of OPTi FireLink/FireBlast Host Controller memory-mapped registers: Offset Size Description (Table 00966) 00h 256 BYTES standard OpenHCI registers (see #00902) 100h DWORD "HceControl" emulation control (see #00967) 104h DWORD "HceInput" legacy Input Buffer (see #00968) 108h DWORD "HceOutput" legacy Output Buffer (see #00969) 10Ch DWORD "HceStatus" legacy Status (see #00970)
See Also: #00902 - #00965
Bitfields for OPTi FireLink/FireBlast "HceControl" register: Bit(s) Description (Table 00967) 31-9 reserved 8 A20 gate state 7 IRQ12 active (write 1 to clear) 6 IRQ1 active (write 1 to clear) 5 A20 gate sequence. 1 D1h written to port 64h. 0 other than D1h written to port 64h 4 external IRQ emulation enable 3 IRQ enable 2 character pending emulation enable 1 (read-only) emulation interrupt condition 0 emulation enable
See Also: #00902 - PORT 0064h
Bitfields for OPTi FireLink/FireBlast "HceInput" register: Bit(s) Description (Table 00968) 31-8 reserved 7-0 data written to port 60h or 64h
See Also: #00902 - #00970 - PORT 0060h - PORT 0064h
Bitfields for OPTi FireLink/FireBlast "HceOutput" register: Bit(s) Description (Table 00969) 31-8 reserved 7-0 data to be returned on read of port 60h
See Also: #00902 - PORT 0060h
Bitfields for OPTi FireLink/FireBlast "HceStatus" register: Bit(s) Description (Table 00970) 31-8 reserved 7 parity error 6 time-out 5 aux output full enable 4 keyboard inhibit switch state. 0 inhibited. 1 not inhibited 3 data written to port:. 0 port 60h. 1 port 64h 2 warm/cold boot flag 1 input full 0 output full
See Also: #00902 - PORT 0060h - PORT 0064h
Category: Expansion Bus Bios - Int 1Ah - P
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