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AX = B10Ah subfn 1106h BH = bus number BL = device/function number (bits 7-3 device, bits 2-0 function) DI = register number (0000h-00FFh) (see #00878)
Return:
CF clear if successful ECX = dword read CF set on error AH = status (00h,87h) (see #00729) EAX, EBX, ECX, and EDX may be modified all other flags (except IF) may be modified
Notes: This function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call. The meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation
See Also: AX=B10Ah - AX=B10Ah/SF=8086h
Format of Via Technologies' VT82C580VPX CPU-PCI bridge configuration: Offset Size Description (Table 00982) 00h 64 BYTEs header (see #00878) (vendor ID 1106h, device ID 0585h) 40h 16 BYTEs unused 50h BYTE cache control 1 51h BYTE cache control 2 52h BYTE non-cacheable control 53h BYTE system performance control 54h BYTE non-cacheable region 1 (high) 55h BYTE non-cacheable region 1 (low) 56h BYTE non-cacheable region 2 (high) 57h BYTE non-cacheable region 2 (low) 58h BYTE DRAM configuration 1 59h BYTE DRAM configuration 2 5Ah 6 BYTEs DRAM row N ending address (N=0-5) 60h BYTE DRAM type 61h BYTE shadow RAM control 1 62h BYTE shadow RAM control 2 63h BYTE shadow RAM control 3 64h BYTE DRAM reference timing 65h BYTE DRAM timing control 1 (see #00996) 66h BYTE DRAM timing control 2 (see #00997) 67h BYTE 32-bit DRAM width (see #00998) 68h BYTE 69h BYTE reserved ("do not program") 6Ah BYTE refresh counter 6Bh BYTE refresh control 6Ch BYTE SDRAM control 6Dh BYTE DRAM control drive strength 6Eh 2 BYTEs reserved 70h BYTE PCI buffer control 71h BYTE CPU-to-PCI flow control 1 72h BYTE CPU-to-PCI flow control 2 73h BYTE PCI master control 1 74h BYTE PCI master control 2 75h BYTE PCI arbitration 1 76h BYTE PCI arbitration 2 77h BYTE reserved for chip test 78h 136 BYTEs reserved !!!via\580vpx.pdf
See Also: #00817
Format of AMD-640 System Controller: Offset Size Description (Table 00983) 00h 64 BYTEs header (see #00878) (vendor ID 1106h, device ID 0595h) 0Dh BYTE latency timer (bits 7-3) 00h = 32*8 PCI clocks 01h = 1*8 PCI clocks N = N*8 PCI clocks 40h 16 BYTEs unused??? 50h BYTE cache control 1 (see #00984) 51h BYTE cache control 2 (see #00985) 52h BYTE non-cacheable control (see #00986) 53h BYTE system performance control (see #00987) 54h WORD non-cacheable region 1 (see #00988) 56h WORD non-cacheable region 2 (see #00988) 58h BYTE DRAM configuration register 1 (see #00989) 59h BYTE DRAM configuration register 2 (see #00990) 5Ah 6 BYTEs end of DRAM banks 0-5 each register specifies bits 29-22 of the bank's ending address 60h BYTE DRAM type (see #00991) 61h BYTE shadow RAM control register 1 (see #00992) 62h BYTE shadow RAM control register 2 (see #00993) 63h BYTE shadow RAM control register 3 (see #00994) 64h BYTE DRAM timing (see #00995) 65h BYTE DRAM control register 1 (see #00996) 66h BYTE DRAM control register 2 (see #00997) 67h BYTE 32-bit DRAM width control register (see #00998) 68h 2 BYTEs reserved 6Ah BYTE DRAM refresh counter (in units of 16 CPU clocks) 6Bh BYTE DRAM refresh control register (see #00999) 6Ch BYTE SDRAM control register (see #01000) 6Dh BYTE DRAM drive strength control register (see #01001) 6Eh BYTE ECC control register (see #01002) 6Fh BYTE ECC status register (see #01003) 70h BYTE PCI buffer control (see #01004) 71h BYTE CPU-to-PCI flow control 1 (see #01005) 72h BYTE CPU-to-PCI flow control 2 (see #01006) 73h BYTE PCI target control (see #01007) 74h BYTE PCI initiator control (see #01008) 75h BYTE PCI arbitration control 1 (see #01009) 76h BYTE PCI arbitration control 2 (see #01010) 77h 137 BYTEs reserved
Note: The AMD-640 uses PCI configuration mechanism #1; bus/device/function are always 00h/00h/00h
See Also: #00817 - #01011
Bitfields for AMD-640 Cache Control Register 1: Bit(s) Description (Table 00984) 7-6 cache enable. 00 disabled. 01 initialization (BIOS fills L2 cache to known state). 10 enabled (normal operation). 11 reserved 5 reserved (do not change) 4-3 tag configuration. 00 eight tag bits, no "modify" bit. 01 seven tag bits, one modify bit. 10 ten tag bits, no modify bit. 11 nine tag bits, one modify bit 2 reserved (0) 1-0 type of cache RAM. 00 none. 01 reserved. 10 burst SRAM. 11 pipeline burst SRAM
See Also: #00983 - #00985
Bitfields for AMD-640 Cache Control Register 2: Bit(s) Description (Table 00985) 7-6 reserved (0) 5 backoff processor until L2 cache filled 4 reserved (0) 3 two banks of SRAM instead of one 2 reserved (0) 1-0 L2 cache size. 00 = 256K. 01 = 512K. 10 = 1M. 11 = 2M
See Also: #00983 - #00984 - #00986
Bitfields for AMD-640 Non-Cacheable Control Register: Bit(s) Description (Table 00986) 7 segment C000h-C7FFh cacheable and write-protected 6 D000h-DFFFh cacheable and write-protected 5 E000h-EFFFh cacheable and write-protected 4 F000h-FFFFh cacheable and write-protected 3 reserved (0) 2 force L2 cache fill 1 reserved (1) 0 L2 write mode (0 = writeback, 1 = write-through)
See Also: #00983 - #00985 - #00987
Bitfields for AMD-640 System Performance Control Register: Bit(s) Description (Table 00987) 7 enable read-around-write 6 enable cache read pipeline cycle 5 enable cache write pipeline cycle 4 enable DRAM pipeline cycle 3 enable PCI Peer Concurrence (PCI initiator can transfer to another PCI device without blocking memory or CPU bus) 2-0 reserved (0)
See Also: #00983 - #00986
Bitfields for AMD-640 Non-Cacheable Region register: Bit(s) Description (Table 00988) 15-11 bits 20-16 of region's base address 10-8 size of non-cacheable area. 000 disabled. 001 = 64K. 010 = 128K. .... 110 = 2M. 111 = 4M 7-0 bits 28-21 of region's base address
See Also: #00983 - #00989
Bitfields for AMD-640 DRAM Configuration Register 1: Bit(s) Description (Table 00989) 7-5 type of address mapping for memory banks 0 and 1. ---EDO/FastPageMode---. 000 eight-bit column address. 001 nine-bit column address. 010 ten-bit column address. 011 eleven-bit column address. 100 twelve-bit column address. Other reserved. ---SDRAM---. 0xx = 16-Mbit SDRAM (see #00991). 1xx = 64-Mbit SDRAM 4 reserved (0) 3-1 type of address mapping ofr memory banks 2 and 3 0 reserved (0)
See Also: #00983 - #00990
Bitfields for AMD-640 DRAM Configuration Register 2: Bit(s) Description (Table 00990) 7-5 type of address mapping for memory banks 4 and 5 (see #00989) 4-3 reserved (0) 2-0 last populated memory bank. 000 - 101 = Bank0 - Bank5. 110,111 reserved
Note: Banks 2-4 are non-cacheable if tag RAM is ten bits + modified bit
See Also: #00983 - #00989
Bitfields for AMD-640 DRAM Type register: Bit(s) Description (Table 00991) 7-6 reserved 5-4 type of DRAM in banks 4 and 5. 00 fast page mode (FPM). 01 extended data out (EDO). 10 reserved. 11 synchronous DRAM (SDRAM) 3-2 type of DRAM in banks 2 and 3 1-0 type of DRAM in banks 0 and 1
See Also: #00983 - #00989 - #00990
Bitfields for AMD-640 Shadow RAM Control Register 1: Bit(s) Description (Table 00992) 7-6 segment CC00h-CFFFh shadow RAM control. 00 shadowing disabled. 01 write enabled. 10 read enabled. 11 both read and write enabled 5-4 segment C800h-CBFFh shadow RAM control 3-2 segment C400h-C7FFh shadow RAM control 1-0 segment C000h-C3FFh shadow RAM control
See Also: #00983 - #00993 - #00994
Bitfields for AMD-640 Shadow RAM Control Register 2: Bit(s) Description (Table 00993) 7-6 segment DC00h-DFFFh shadow RAM control. 00 shadowing disabled. 01 write enabled. 10 read enabled. 11 both read and write enabled 5-4 segment D800h-DBFFh shadow RAM control 3-2 segment D400h-D7FFh shadow RAM control 1-0 segment D000h-D3FFh shadow RAM control
See Also: #00983 - #00992 - #00994
Bitfields for AMD-640 Shadow RAM Control Register 3: Bit(s) Description (Table 00994) 7-6 segment E000h-EFFFh shadow RAM control. 00 shadowing disabled. 01 write enabled. 10 read enabled. 11 both read and write enabled 5-4 segment F000h-FFFFh shadow RAM control 3-2 ISA memory hole. 00 none. 01 = 512K-640K. 10 = 15M-16M. 11 = 14M-16M 1 enable SMI redirection.
If set:
30000h-3FFFFh redirected to B0000h, 40000h-4FFFFh to A0000h 0 redirect video RAM accesses (A0000h-BFFFFh) to system DRAM rather than PCI bus (used to initialize SMRAM at B0000h)
See Also: #00983 - #00992 - #00993
Bitfields for AMD-640 DRAM Timing register: Bit(s) Description (Table 00995) 7-6 RAS# precharge time. 00 = 2T (for 50ns DRAM) [T = HCLK period]. 01 = 3T (60ns). 10 = 4T (70ns). 11 = 6T 5-4 RAS# pulse width. 00 = 3T (for 50ns DRAM). 01 = 4T (60ns). 10 = 5T (70ns). 11 = 6T 3-2 CAS# pulse width.
FPM:
00=1T, 01=2T, 10=3T, 11=4T.EDO:
00=4T, 01=1T, 10=2T, 11=3T 1 write pulse width (0 = 1T, 1 = 2T) 0 delay from column address to CAS# (0 = 1T, 1 = 2T)
See Also: #00983 - #00994
Bitfields for AMD-640 DRAM Control Register 1: Bit(s) Description (Table 00996) 7-6 page mode control. 00 close page after access. 01 reserved. 10 keep page open until timeout or page miss. 11 close page if processor has not accessed DRAM for 8 CPU cycles 5 enable fast DRAM decoding 4 reduce EDO DRAM leadoff cycle from 6T to 5T 3 delay DRAM data latch by 1/2 clock 2 (AMD-640) reserved. (VT82C580VPX) Pin88 function (0 = DB32, 1 = TA9) 1 reserved (0) 0 delay DRAM read cycle by 1T whenever write buffer contains data. Must be set if read-around-write is enabled (see #00987)
See Also: #00983 - #00997 - #00982
Bitfields for AMD-640 DRAM Control Register 2: Bit(s) Description (Table 00997) 7 enable EDO test mode. When set, EDO RAM contents will read correctly, FPM not 6 reserved (0) 5-3 (AMD-640) reserved (0) 5 (VT82C580VPX) SDRAM CAS# latency (0 = latency 2, 1 = latency 3) 4 (VT82C580VPX) reserved (0) 3 (VT82C580VPX) enable Turbo EDO mode (0 = x-2-2-2, 1 = x-1-1-1 bursts) 2 add one wait state for memory data-to-host data pop 1 reduce RAS# precharge by 1T for SDRAM 0 reduce RAS# to CAS# delay for SDRAM
Note: Bits 1 and 0 have no effect unless SDRAM has been selected via the DRAM type register (see #00991)
See Also: #00983 - #00996 - #00982
Bitfields for AMD-640 32-bit DRAM Width Control register: Bit(s) Description (Table 00998) 7 RAS# to Column Address delay (0 = 1T, 1 = 2T) 6 delay NA# by 1T 5-0 widths of banks 5 - 0. AMD-640 documentation clains that all bits should be cleared. For VT82C580VPX, settings are 0 = 64-bit, 1 = 32-bit (only applicable when two banks of PBSRAM are installed)
See Also: #00983 - #00982 - #00997 - #00999
Bitfields for AMD-640 DRAM Refresh Control register: Bit(s) Description (Table 00999) 7 enable CAS#-before-RAS# refresh 6 enable burst refresh (four rows every 60 us, not one every 15 us) 5-0 reserved (0)
See Also: #00983 - #00998
Bitfields for AMD-640 SDRAM Control Register: Bit(s) Description (Table 01000) 7 enable 4-bank interleave for 64-Mbit SDRAMs (when bit 5 set) 6 enable SDRAM burst write 5 enable SDRAM bank interleave. (when set, reduces 3-line burst from 8-1-1-1-3-1-1-1-3-1-1-1 to 8-1...) 4 reserved (0) 3 SDRAM CAS# latency (0 = latency 2, 1 = latency 3) 2-0 SDRAM Operation Mode. 000 normal SDRAM. 001 enable NOP command. 010 convert CPU-to-DRAM cycles into All Banks Precharge command. 011 convert CPU-to-DRAM cycles into commands on MA[11:0]. 100 enable CAS#-before-RAS# cycles. Other reserved
See Also: #00983 - #00999
Bitfields for AMD-640 DRAM Drive Strength Control register: Bit(s) Description (Table 01001) 7 bank decoding test (1="for production test only. DO NOT SET.") 6 strength of MA[1:0] drive (0 = 12ma, 1 = 24ma) 5 function of N17 and M17 pins. 0 N17 is RAS5#, M17 is RAS4#. 1 N17 is MA1, M17 is MA0 4 force SMM mode (when set, act as if SMIACT# is asserted) 3 strength of SDRAM command lines (0 = 12ma, 1 = 24ma) 2 strength of MA[13:2] and WEx# drive (0 = 12ma, 1 = 24ma) 1 strength of CAS# drive (0 = 12ma, 1 = 24ma) 0 strength of RAS# drive (0 = 12ma, 1 = 24ma)
See Also: #00983 - #00999
Bitfields for AMD-640 ECC Control Register: Bit(s) Description (Table 01002) 7 ECC mode select (0 = parity, 1 = ECC) 6 reserved (0) 5 assert SERR# for ECC multibit errors 4 assert SERR# for ECC single-bit errors 3 add 1T for SDRAM read cycles with ECC (required when ECC mode enabled) 2 enable ECC for banks 5 and 4 1 enable ECC for banks 3 and 2 0 enable ECC for banks 1 and 0
See Also: #00983 - #01003
Bitfields for AMD-640 ECC Status Register: Bit(s) Description (Table 01003) 7 multi-bit error detected (write-clear) 6-4 number of DRAM bank containing multi-bit error (write-clear) 3 single-bit error detected (write-clear) 2-0 number of DRAM bank containing single-bit error (write-clear)
See Also: #00983 - #01002
Bitfields for AMD-640 PCI Buffer Control register: Bit(s) Description (Table 01004) 7 enable CPU-to-PCI posted writes 6 enable PCI-to-DRAM posted writes 5 enable PCI-to-DRAM prefetch 4-2 reserved (0) 1 disable PCI retry for processor QuadWord access 0 CPU-to-PCI buffer flushing. 0 flushing has priority over bus grants. 1 bus-grant to another PCI initiator has priority over flushing
See Also: #00983
Bitfields for AMD-640 CPU-to-PCI Flow Control 1 register: Bit(s) Description (Table 01005) 7,3 PCI burst control. 00 no bursts, every write goes to write buffer. 01 burst writes placed in write buffer, non-burst writes sent to PCI bus immediately after write buffers flushed. 1x all writes go to write buffer; bursting performed for burstable transactions 6 enable byte merge 5 reserved (1) 4 enable posted PCI I/O cycle writes 2 eanble fast back-to-back PCI writes 1 enable quick frame generation (FRAME# asserted one clock early) 0 add one wait state to IRDY#
See Also: #00983 - #01006
Bitfields for AMD-640 CPU-to-PCI Flow Control 2 register: Bit(s) Description (Table 01006) 7 unsuccessful retry (16 or 64 times) has occurred (write-clear) 6 retry timeout action. 0 retry continuously, recording status. 1 flush buffer; if reading, return FFFFFFFFh 5-4 retry count and backoff. 00 retry twice, backoff processor. 01 retry 16 times, set bit 7 on failure. 10 retry four times, backoff processor. 11 retry 64 times, set bit 7 on failure 3 discard failed data from write buffer when retry fails 2 backoff processor if PCI read retry fails 1 assert FRAME# one cycle earlier than indicated by offset 71h bit 1 0 reduce TRDY#-to-BRDY# by one HCLK on processor reads of PCI target
See Also: #00983 - #01005 - #01007
Bitfields for AMD-640 PCI Target Control register: Bit(s) Description (Table 01007) 7 slow memory decoding (must be set if fast back-to-back cycles enabled) 6 add one wait state to TRDY# response on reads 5 add one wait state to TRDY# response on writes 4 reserved (0) 3 assert STOP# after write timeout 2 assert STOP# after read timeout 1 enable sampling of PCI LOCK# pin 0 force AMD-640 to initiate PCI arbitration if FRAM# not asserted within 16 PCI clocks of last GNT#
See Also: #00983 - #01006 - #01008
Bitfields for AMD-640 PCI Initiator Control register: Bit(s) Description (Table 01008) 7 enable enhanced PCI commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) 6 enable single-write byte merging 5-0 reserved (0)
See Also: #00983 - #01007 - #01008
Bitfields for AMD-640 PCI Arbitration Control 1 register: Bit(s) Description (Table 01009) 7 arbitration priority. 0 = fixed (high-to-low is REQ1#, REQ2#, REQ3#, REQ4#, PREQ#, and CPU). 1 = fair (round-robin) arbitration 6 arbitration mode. 0 arbitrate at end of REQ#. 1 arbitrate at end of each FRAME# (allows pre-emption by a higher-priority initiator) 5-4 reserved (0) 3-0 number of idle time periods of 32 PCI clocks before arbitration is forced (0000 disables timeout)
See Also: #00983 - #01008 - #01010
Bitfields for AMD-640 PCI Arbitration Control 2 register: Bit(s) Description (Table 01010) 7 enable initiator priority rotation. =0 use arbitration priority as set by offset 75h bit 7 (see #01009) 6 reserved (0) 5-4 initiator priority rotation control. 00 disabled (use offset 75h bit 7 setting). 01 grant to processor after every PCI initiator grant. 10 grant to processor after every other PCI initiator grant. 11 grant to processor after every three PCI initiator grants 3-0 reserved (0)
See Also: #00983 - #01009
Format of AMD-645 Peripheral Bus Controller, function 0 (PCI-ISA bridge) data: Offset Size Description (Table 01011) 00h 64 BYTEs header (see #00878) (vendor ID 1106h, device ID 0586h) 40h BYTE ISA bus control (see #01012) 41h BYTE ISA Test Mode (see #01013) 42h BYTE ISA clock control (see #01014) 43h BYTE ROM Decode Control (see #01015) 44h BYTE keyboard controller control (see #01016) 45h BYTE Type F DMA control (see #01017) 46h BYTE Miscellaneous control 1 (see #01018) 47h BYTE Miscellaneous control 2 (see #01019) 48h BYTE Miscellaneous control 3 (see #01020) 49h BYTE reserved 4Ah BYTE IDE interrupt routing (see #01021) 4Bh BYTE reserved 4Ch BYTE PCI memory hole bottom, bits 23-16 4Dh BYTE PCI memory hole top, bits 23-16 (if top is <= bottom, hole is disabled) 4Eh WORD DMA/Master memory access control 3 (see #01022) 50h BYTE PnP DRQ Routing (see #01023) 51h 3 BYTEs reserved 54h BYTE PCI IRQ Edge/Level selection (see #01024) 55h BYTE PnP Routing for external MIRQ0/1 (see #01025) 56h BYTE PnP Routing for PCI INTB/INTA (see #01027) 57h BYTE PnP Routing for PCI INTD/INTC (see #01028) 58h BYTE PnP Routing for external MIRQ2 (see #01029) 59h BYTE MIRQ pin configuration (see #01030) 5Ah BYTE XD Power-On Strap Options (see #01031) 5Bh BYTE internal RTC test mode (see #01032) 5Ch 4 BYTEs reserved 60h WORD distributed DMA, channel 0 base address/enable (see #01033) 62h WORD distributed DMA, channel 1 base address/enable (see #01033) 64h WORD distributed DMA, channel 2 base address/enable (see #01033) 66h WORD distributed DMA, channel 3 base address/enable (see #01033) 68h WORD reserved 6Ah WORD distributed DMA, channel 5 base address/enable (see #01033) 6Ch WORD distributed DMA, channel 6 base address/enable (see #01033) 6Eh WORD distributed DMA, channel 7 base address/enable (see #01033) 70h 144 BYTEs reserved
See Also: #00817 - #00983 - #01034 - #01046
Bitfields for AMD-645 ISA Bus Control register: Bit(s) Description (Table 01012) 7 extra delay on ISA commands (default is disabled) 6 enable extended ISA bus ready (default is disabled) 5 ISA slave wait states (0=4 wait states [default], 1=5 wait states) 4 chipset I/O wait states (0=2 wait states [default], 1=4 wait states) 3 I/O recovery time enabled 2 enable extended ALE 1 no ROM wait states (default is clear, 1 wait state) 0 enable ROM writes
See Also: #01011
Bitfields for AMD-645 ISA Test Mode register: Bit(s) Description (Table 01013) 7-6 reserved (0) 5 enable fast reset via PORT 0092h 4 reserved (0) 3 double DMA clock (=0 DMA at 1/2 ISA clock, =1 DMA at full ISA clock) 2-0 reserved (0)
See Also: #01011 - #01012 - #01014
Bitfields for AMD-645 ISA Clock Control register: Bit(s) Description (Table 01014) 7 disable "Latch IO16#" 6-4 reserved (0) 3 enable ISA Bus clock select via bits 2-0 (=0 use PCLK/4) 2-0 ISA Bus clock select. 000 PCLK/3 (default). 001 PCLK/2. 010 PCLK/4. 011 PCLK/6. 100 PCLK/5. 101 PCLK/10. 110 PCLK/12. 111 OSC/2
Note: In order to safely change the ISA clock, bit 3 must first be cleared, then bits 2-0 may be changed, and finally bit 3 can be set again
See Also: #01011 - #01013
Bitfields for AMD-645 ROM Decode Control register: Bit(s) Description (Table 01015) 7 enable 64K ROM at FFFE00000h-FFFEFFFFh 6 enable 384K ROM at FFF80000h-FFFDFFFFh 5 enable 32K ROM at E8000h-EFFFFh 4 enable 32K ROM at E0000h-E7FFFh 3 enable 32K ROM at D8000h-D8FFFh 2 enable 32K ROM at D0000h-D7FFFh 1 enable 32K ROM at C8000h-CFFFFh 0 enable 32K ROM at C0000h-C7FFFh
See Also: #01011
Bitfields for AMD-645 Keyboard Controller Control register: Bit(s) Description (Table 01016) 7-4 reserved (0) 3 enable Mouse Lock 2-0 reserved (0)
See Also: #01011
Bitfields for AMD-645 Type-F DMA Control register: Bit(s) Description (Table 01017) 7 enable line buffer from ISA Master/DMA to PCI 6-4 enable Type F timing on DMA Channels 7, 6, 5 3-0 enable Type F timing on DMA Channels 3-0
See Also: #01011
Bitfields for AMD-645 Miscellaneous Control 1 register: Bit(s) Description (Table 01018) 7-5 reserved (0) 4 enable command register test mode. (when set, PCI offset 04h bits 0-1 become writable and bit 3 read-only) 3-2 reserved (0) 1 disallow interruptions of PCI burst reads 0 enable posted memory writes
See Also: #01011 - #01019 - #01020
Bitfields for AMD-645 Miscellaneous Control 2 register: Bit(s) Description (Table 01019) 7 use INIT as CPU reset signal instead of CPURST 6 enable PCI transaction delay 5 enable ports 04D0h-04D1h (per EISA spec) 4 enable interrupt controller shadow register 3 reserved (0) 2 enable write delay transaction time-out timer 1 enable read delay transaction time-out timer 0 software PCI reset -- set to cause a PCI reset via PCIRST pin
See Also: #01011 - #01018 - #01020 - PORT 04D0h
Bitfields for AMD-645 Miscellaneous Control 3 register: Bit(s) Description (Table 01020) 7-4 reserved (0) 3 disable RTC PORT 0074h and PORT 0075h 2 disable integrated USB controller 1 disable integrated IDE controller 0 add 512K to offset 4Eh bits 15-12 at top of PCI memory
See Also: #01011 - #01018 - #01019 - PORT 0074h"AMD-645"
Bitfields for AMD-645 IDE Interrupt Routing register: Bit(s) Description (Table 01021) 7 wait for PGNT before Grant to ISA Master/DMA 6 port 00xxh bus select (0=access via SD bus, 1=access via XD bus) 5-4 reserved (0) 3-2 secondary IDE channel IRQ (same encoding as primary) 1-0 primary IDE channel IRQ. 00 IRQ14 (default for primary). 01 IRQ15 (default for secondary). 10 IRQ10. 11 IRQ11
See Also: #01011
Bitfields for AMD-645 DMA/Master Memory Access Control 3 register: Bit(s) Description (Table 01022) 15-12 top of PCI memory for ISA DMA/Master access, bits 23-20, less 1 11 accesses to E0000h-EFFFFh forwarded to PCI 10 accesses to A0000h-BFFFFh forwarded to PCI 9 accesses to 80000h-9FFFFh forwarded to PCI 8 accesses to 00000h-7FFFFh forwarded to PCI 7 accesses to DC000h-DFFFFh forwarded to PCI 6 accesses to D8000h-DBFFFh forwarded to PCI 5 accesses to D4000h-D7FFFh forwarded to PCI 4 accesses to D0000h-D3FFFh forwarded to PCI 3 accesses to CC000h-CFFFFh forwarded to PCI 2 accesses to C8000h-CBFFFh forwarded to PCI 1 accesses to C4000h-C7FFFh forwarded to PCI 0 accesses to C0000h-C3FFFh forwarded to PCI
See Also: #01011
Bitfields for AMD-645 PnP DRQ Routing register: Bit(s) Description (Table 01023) 7-0 reserved (always read 04h)
See Also: #01011 - #01024
Bitfields for AMD-645 PCI IRQ Edge/Level Select register: Bit(s) Description (Table 01024) 7-4 reserved 3 PIRQA# is edge-sensitive rather than level-sensitive 2 PIRQB# is edge-sensitive 1 PIRQC# is edge-sensitive 0 PIRQD# is edge-sensitive
See Also: #01011 - #01023 - #01025
Bitfields for AMD-645 PnP IRQ Routing 1 register: Bit(s) Description (Table 01025) 7-4 routing for MIRQ1 (see #01026) 3-0 routing for MIRQ0 (see #01026)
See Also: #01011 - #01024
(Table 01026) Values for AMD-645 IRQ routing: 0000 disabled 0001 IRQ1 0010 reserved 0011 IRQ3 ... 0111 IRQ7 1000 reserved 1001 IRQ9 ... 1100 IRQ12 1101 reserved 1110 IRQ14 1111 IRQ15
See Also: #01025 - #01027 - #01028 - #01029
Bitfields for AMD-645 PnP IRQ Routing 2 register: Bit(s) Description (Table 01027) 7-4 routing for PIRQB# (see #01026) 3-0 routing for PIRQA# (see #01026)
See Also: #01025 - #01028 - #01029
Bitfields for AMD-645 PnP IRQ Routing 3 register: Bit(s) Description (Table 01028) 7-4 routing for PIRQD# (see #01026) 3-0 routing for PIRQC# (see #01026)
See Also: #01025 - #01027 - #01029
Bitfields for AMD-645 PnP IRQ Routing 4 register: Bit(s) Description (Table 01029) 7-4 reserved 3-0 routing for MIRQ2# (see #01026)
See Also: #01025 - #01027 - #01028
Bitfields for AMD-645 MIRQ Pin Configuration register: Bit(s) Description (Table 01030) 7-3 reserved (0) 2 select MASTER# instead of MIRQ2 1 select KEYLOCK instead of MIRQ1 0 select APICCS# instead of MIRQ0
See Also: #01011 - #01029
Bitfields for AMD-645 XD Power-Up Strap Options register: Bit(s) Description (Table 01031) 7-4 Keyboard RP16-RP13 3 reserved (0) 2 enable internal RTC 1 enable internal PS/2 mouse 0 enable internal keyboard controller
Note: The default value of this register is latched from external pins at power-up
See Also: #01011
Bitfields for AMD-645 Internal RTC Test Mode register: Bit(s) Description (Table 01032) 7-2 reserved (0) 1 enable access to internal RTC's RAM when RTC is disabled (see PORT 0074h"AMD-645") 0 reserved (0)
See Also: #01011
Bitfields for AMD-645 Distributed DMA Base/Enable register: Bit(s) Description (Table 01033) 15-4 base address bits 15-4 for Channel N 3 enable DMA channel 2-0 reserved (0)
See Also: #01011
Format of AMD-645 Peripheral Bus Controller, function 1 (IDE Control) data: Offset Size Description (Table 01034) 00h 64 BYTEs header (see #00878) (vendor ID 1106h [VIA Technologies], device ID 0571h) 09h BYTE programming interface
bit 7:
Master IDE capabilitybits 6-4:
Reserved (0)bit 3:
Secondary channel supports operating mode selectionbit 2:
Use native PCI mode, not compatibility mode for sec. ch.bit 1:
Primary channel supports operating mode selectionbit 0:
Use native PCI mode, not compatibility mode for pri. ch. 10h DWORD primary data/command base address 14h DWORD primary control/status base address 18h DWORD secondary data/command base address 1Ch DWORD secondary control/status base address 20h DWORD bus master control base address (default 0000CC01h) 40h BYTE chip enable (see #01035) 41h BYTE IDE configuration (see #01036) 42h BYTE reserved ("do not program") 43h BYTE FIFO configuration (see #01037) 44h BYTE miscellaneous control 1 (see #01038) 45h BYTE miscellaneous control 2 (see #01039) 46h BYTE miscellaneous control 3 (see #01040) 47h BYTE unused??? 48h DWORD drive timing control (see #01041) 4Ch BYTE address setup time (see #01042) 4Dh BYTE reserved ("do not program") 4Eh BYTE secondary non-01F0h port access timing (see #01043) 4Fh BYTE primary non-01F0h port access timing (see #01043) 50h BYTE UltraDMA/33 extended timing control, Sec. Drive 1 (see #01044) 51h BYTE UltraDMA/33 extended timing control, Sec. Drive 0 (see #01044) 52h BYTE UltraDMA/33 extended timing control, Pri. Drive 1 (see #01044) 53h BYTE UltraDMA/33 extended timing control, Pri. Drive 0 (see #01044) 54h 4 BYTEs reserved 58h DWORD "reserved" (appears to be an additional set of drive timing controls) 5Ch 4 BYTEs ??? 60h WORD primary sector size (see #01045) 62h 6 BYTEs reserved 68h WORD secondary sector size (see #01045) 6Ah 150 BYTEs reserved
Note: The AMD-645 IDE controller is compatible with the SFF 8038i v1.0 spec
See Also: #00817 - #01011 - #01046
Bitfields for AMD-645 IDE Chip Enable register: Bit(s) Description (Table 01035) 7-2 reserved (00001) 1 enable primary IDE channel 0 enable secondary IDE channel
See Also: #01034 - #01036
Bitfields for AMD-645 IDE Configuration register : Bit(s) Description (Table 01036) 7 enable primary IDE read-prefetch buffer 6 enable primary IDE post write buffer 5 enable secondary IDE read-prefetch buffer 4 enable secondary IDE post write buffer 3-0 reserved (0110)
See Also: #01034 - #01035 - 3813
Bitfields for AMD-645 IDE FIFO Configuration register: Bit(s) Description (Table 01037) 7 reserved (0) 6-5 FIFO configuration. 00 primary channel = 16, secondary channel = 0. 01/10 primary channel = 8, secondary channel = 8. 11 primary channel = 0, secondary channel = 16 4 reserved (1) 3-2 primary channel FIFO threshold. 00 = completely full. 01 = 3/4 full. 10 = 1/2 full. 11 = 1/4 full 1-0 secondary channel FIFO threshold (same settings as bits 3-2)
See Also: #01034 - #01036
Bitfields for AMD-645 IDE Miscellaneous Control 1 register: Bit(s) Description (Table 01038) 7 reserved (0) 6 number of wait states on Master Read Cycle IRDY# 5 number of wait states on Master Write Cycle IRDY# 4 enable 1/2 clock advance on FIFO output 3 enable bus-master IDE status register read retry 2-0 reserved (0)
See Also: #01034 - #01039 - #01040
Bitfields for AMD-645 IDE Miscellaneous Control 2 register: Bit(s) Description (Table 01039) 7 reserved (0) 6 swap interrupts between the two IDE channels 5-0 reserved (0)
See Also: #01034 - #01038 - #01040
Bitfields for AMD-645 IDE Miscellaneous Control 3 register: Bit(s) Description (Table 01040) 7 enable FIFO flush for read DMA on primary channel interrupt 6 enable FIFO flush for read DMA on secondary channel interrupt 5 enable FIFO flush for each sector on primary channel 4 enable FIFO flush for each sector on secondary channel 3-2 reserved 1-0 maximum DRDY# pulse width. 00 unlimited. 01 64 PCI clocks. 10 128 PCI clocks. 11 192 PCI clocks
See Also: #01034 - #01038 - #01039
Bitfields for AMD-645 IDE Drive Timing Control register: Bit(s) Description (Table 01041) 31-28 primary drive 0 active DIOR#/DIOW# pulse width 27-24 primary drive 0 DIOR#/DIOW# recovery time (PCI clocks, less 1) 23-20 primary drive 1 active pulse width (PCI clocks, less 1) 19-16 primary drive 1 recovery time 15-12 secondary drive 0 active pulse width 11-8 secondary drive 0 recovery time 7-4 secondary drive 1 active pulse width 3-0 secondary drive 1 recover time (PCI clocks, less 1)
See Also: #01034 - #01042
Bitfields for AMD-645 IDE Address Setup Time register: Bit(s) Description (Table 01042) 7-6 primary drive 0 address setup time. 00 = 1T. 01 = 2T. 10 = 3T. 11 = 4T 5-4 primary drive 1 address setup time (same values as above) 3-2 secondary drive 0 address setup time 1-0 secondary drive 1 address setup time
See Also: #01034 - #01041
Bitfields for AMD-645 Non-01F0h Port Access Timing register: Bit(s) Description (Table 01043) 7-4 width of DIOR#/DIOW# active pulse in PCI clocks (less 1) 3-0 DIOR#/DIOW# recovery time in PCI clocks (less 1)
See Also: #01011
Bitfields for AMD-645 UltraDMA/33 Extended Timing Control register: Bit(s) Description (Table 01044) 7 method for enabling UltraDMA mode on drive. 0 using "Set Feature" command. 1 using bit 6 of this register 6 enable UltraDMA mode for drive 5 UltraDMA transfer mode. 0 UltraDMA DMA mode. 1 UltraDMA PIO mode 4-2 reserved (0) 1-0 drive cycle time. 00 = 2T. .... 11 = 5T
See Also: #01011
Bitfields for AMD-645 Sector Size register: Bit(s) Description (Table 01045) 15-12 reserved 11-0 sector size in bytes (default 200h)
See Also: #01011
Format of AMD-645 Peripheral Bus Controller, function 2 (USB Controller) data: Offset Size Description (Table 01046) 00h 64 BYTEs header (see #00878) (vendor ID 1106h, device ID 3038h) 20h DWORD base address of USB I/O ports (see PORT xxxxh"AMD-645 - USB" 40h BYTE miscellaneous control 1 (see #01047) 41h BYTE miscellaneous control 2 (see #01048) 42h 2 BYTEs reserved 44h 3 BYTEs reserved ("do not program") 47h BYTE reserved 48h 24 BYTEs reserved 60h BYTE USB release number (read-only, 10h) 61h 95 BYTEs reserved C0h WORD USB legacy support (read-only, 2000h) C2h 62 BYTEs reserved
See Also: #00817 - #00983 - #01011 - #01034 - #01049
Bitfields for AMD-645 USB Miscellaneous Control 1 register: Bit(s) Description (Table 01047) 7 PCI memory commands. 0 support memory-read-line, memory-read-multiple, and memory-write-and-invalidate. 1 memory read and memory write commands only 6 do not disable port on EOF babble 5 eanble PCI parity checking and PERR# generation 4 reserved (0) 3 USB data length. 0 allow TD length up to 1280 bytes. 1 limit to 1023 2 enable USB power management 1 DMA limited to 8-DW burst instead of 16-DW 0 insert one PCI wait state
See Also: #01046 - #01048
Bitfields for AMD-645 USB Miscellaneous Control 2 register: Bit(s) Description (Table 01048) 7-3 reserved (0) 2 only trap port 60h/64h bits when trap-enable bits are set 1 do not pass A20GATE command sequence (from UHCI) through I/O port 64h 0 reserved (0)
See Also: #01046 - #01047 - PORT 0064h
Format of AMD-645 Peripheral Bus Controller, function 3 (Power Mgmt) data: Offset Size Description (Table 01049) 00h 64 BYTEs header (see #00878) (vendor ID 1106h, device ID 3040h) 20h DWORD base address for I/O ports (see PORT xxxxh"AMD-645") 40h BYTE pin configuration (see #01050) 41h BYTE general configuration (see #01051) 42h BYTE SCI interrupt configuration (see #01052) 43h BYTE reserved 44h WORD primary interrupt channel bit 2 is reserved; setting any other bit N makes IRQN the primary interrupt channel 46h WORD secondary interrupt channel bit 2 is reserved; setting any other bit N makes IRQN the secondary interrupt channel 48h 8 BYTEs unused??? 50h DWORD GP timer control (see #01053) 54h 13 BYTEs reserved 61h BYTE programming interface read value (value to be returned by configuration register 09h) (write-only) 62h BYTE subclass read value (value to be returned by configuration register 0Ah) (write-only) 63h BYTE base class read value (value to be returned by configuration register 0Bh) (write-only) 64h 156 BYTEs reserved
See Also: #00817 - #00983 - #01011 - #01034 - #01046 - #01049
Bitfields for AMD-645 PM Pin Configuration register: Bit(s) Description (Table 01050) 7 GPIO4 configuration (0 = Pin136 is GPO_WE, 1 = Pin136 is GPIO4) 6 GPIO3 configuration (0 = Pin92 is GPI_RE#, 1 = Pin92 is GPIO3) 5-0 reserved (0)
See Also: #01049 - #01051
Bitfields for AMD-645 PM General Configuration register: Bit(s) Description (Table 01051) 7 enable debounce of PWRBTN# input 6 enable ACPI timer reset 5-4 reserved ("do not program") 3 select ACPI timer size (0 = 24 bits, 1 = 32 bits) 2 enable PCI Frame Activation as Resume Event im power state C2 1 clock-throttling cycle time. 0 = 32 usec clock, 512 usec cycle time (default). 1 = 1 msec clock 16 msec cycle time 0 reserved ("do not program")
See Also: #01049 - #01050 - MEM xxxxh:xxx0h"ACPI"
Bitfields for AMD-645 PM SCI Interrupt Configuration register: Bit(s) Description (Table 01052) 7-4 reserved (0) 3-0 interrupt assignment. 0000 disabled. Else IRQ number (except IRQ2 is reserved)
See Also: #01049
Bitfields for AMD-645 PM GP Timer Control register: Bit(s) Description (Table 01053) 31-30 power-conservation mode timer. 00 = 1/16 sec. 01 = 1/8 sec. 10 = 1 sec. 11 = 1 minute 29 (read) set when system is in power-conservation mode 28 enable power-conservation mode 27-26 secondary event timer. 00 = 2 msec. 01 = 64 msec. 10 = 1/2 sec. 11 = 0.25 msec after EOI 25 secondary event occurred, secondary event timer is counting down 24 enable secondary event timer 23-16 GP1 Timer count (see bits 5-4) 15-8 GP0 Timer count (see bits 1-0) 7 start GP1 timer 6 automatically reload GP1 timer after counting down to 0 5-4 time base for GP1 timer. 00 disabled. 01 = 32 microseconds. 10 = 1 second. 11 = 1 minute 3 start GP0 timer 2 automatically reload GP0 timer after counting down to 0 1-0 time base for GP0 timer. 00 disabled. 01 = 1/16 second. 10 = 1 second. 11 = 1 minute
See Also: #01049
Category: Expansion Bus Bios - Int 1Ah - P
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